component
74HCT373PW
Public Made by Adomby adom
Nexperia Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"title": "74HCT373PW",
"brief": "Nexperia Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"package": "TSSOP-20",
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"category": "Logic",
"subcategory": "Latches",
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"number": "1",
"name": "OE",
"type": "input",
"description": "Active-LOW 3-state output enable; a HIGH forces outputs Q0 to Q7 into the high-impedance OFF-state without affecting the latch contents."
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{
"number": "2",
"name": "Q0",
"type": "tri_state",
"description": "3-state latch output that goes high-impedance when OE is HIGH."
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{
"number": "3",
"name": "D0",
"type": "input",
"description": "Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V)."
},
{
"number": "4",
"name": "D1",
"type": "input",
"description": "Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V)."
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{
"number": "5",
"name": "Q1",
"type": "tri_state",
"description": "3-state latch output that goes high-impedance when OE is HIGH."
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"name": "Q2",
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"description": "3-state latch output that goes high-impedance when OE is HIGH."
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"number": "7",
"name": "D2",
"type": "input",
"description": "Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V)."
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{
"number": "8",
"name": "D3",
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"description": "Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V)."
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{
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{
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"name": "GND",
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"description": "Ground reference (0 V) for all voltages on the device."
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{
"number": "11",
"name": "LE",
"type": "input",
"description": "Active-HIGH latch enable; when HIGH the latches are transparent, and when LOW they store the data present at the inputs."
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{
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"description": "3-state latch output that goes high-impedance when OE is HIGH."
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"number": "13",
"name": "D4",
"type": "input",
"description": "Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V)."
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{
"number": "14",
"name": "D5",
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"description": "Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V)."
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{
"number": "15",
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"description": "3-state latch output that goes high-impedance when OE is HIGH."
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{
"number": "16",
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"description": "3-state latch output that goes high-impedance when OE is HIGH."
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"number": "17",
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"number": "18",
"name": "D7",
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"description": "Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V)."
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{
"number": "19",
"name": "Q7",
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"source_page": 6,
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"source_page": 6,
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"name": "input capacitance",
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"min": null,
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"name": "propagation delay Dn to Qn",
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"source_page": 7,
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"name": "propagation delay LE to Qn",
"symbol": "tpd",
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"min": null,
"typ": 16,
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"conditions": "LE to Qn; see Fig. 9; VCC = 4.5 V",
"source_page": 7,
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"name": "enable time OE to Qn",
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"name": "propagation delay LE to Qn",
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