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74HCT373PW

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Nexperia Latches, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HCT373PW

Nexperia · Latches · TSSOP-20

74HCT373PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-LOW 3-state output enable; a HIGH forces outputs Q0 to Q7 into the high-impedance OFF-state without affecting the latch contents.
2 Q0 tri_state 3-state latch output that goes high-impedance when OE is HIGH.
3 D0 input Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V).
4 D1 input Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V).
5 Q1 tri_state 3-state latch output that goes high-impedance when OE is HIGH.
6 Q2 tri_state 3-state latch output that goes high-impedance when OE is HIGH.
7 D2 input Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V).
8 D3 input Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V).
9 Q3 tri_state 3-state latch output that goes high-impedance when OE is HIGH.
10 GND power_in Ground reference (0 V) for all voltages on the device.
11 LE input Active-HIGH latch enable; when HIGH the latches are transparent, and when LOW they store the data present at the inputs.
12 Q4 tri_state 3-state latch output that goes high-impedance when OE is HIGH.
13 D4 input Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V).
14 D5 input Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V).
15 Q5 tri_state 3-state latch output that goes high-impedance when OE is HIGH.
16 Q6 tri_state 3-state latch output that goes high-impedance when OE is HIGH.
17 D6 input Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V).
18 D7 input Data input to the latch; for 74HCT373 it is TTL level (VIH minimum 2.0 V, VIL maximum 0.8 V at VCC 4.5 V to 5.5 V).
19 Q7 tri_state 3-state latch output that goes high-impedance when OE is HIGH.
20 VCC power_in Supply voltage; the 74HCT373 recommended range is 4.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 4
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
output current IO -35 35 mA VO = -0.5 V to (VCC + 0.5 V) 4
supply current ICC 70 mA 4
ground current IGND -70 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW 4
supply voltage (74HCT373) VCC 4.5 5 5.5 V 5
input voltage VI 0 V 5
output voltage VO 0 V 5
ambient temperature Tamb -40 25 125 °C 5
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 5
HIGH-level input voltage VIH 2 1.6 V VCC = 4.5 V to 5.5 V 6
LOW-level input voltage VIL 1.2 0.8 V VCC = 4.5 V to 5.5 V 6
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V 6
HIGH-level output voltage VOH 3.7 4.32 V VI = VIH or VIL; IO = -6.0 mA; VCC = 4.5 V 6
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 4.5 V 6
LOW-level output voltage VOL 0.16 0.4 V VI = VIH or VIL; IO = 6.0 mA; VCC = 4.5 V 6
input leakage current II -1 1 μA VI = VCC or GND; VCC = 5.5 V 6
OFF-state output current IOZ -10 10 μA VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND 6
supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V 6
additional supply current (Dn input) ΔICC 30 147 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A 6
additional supply current (LE input) ΔICC 150 735 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A 6
additional supply current (OE input) ΔICC 100 490 μA VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A 6
input capacitance CI 3.5 pF 6
propagation delay Dn to Qn tpd 17 45 ns Dn to Qn; see Fig. 8; VCC = 4.5 V 7
propagation delay LE to Qn tpd 16 48 ns LE to Qn; see Fig. 9; VCC = 4.5 V 7
enable time OE to Qn ten 19 48 ns OE to Qn; see Fig. 10; VCC = 4.5 V 7
disable time OE to Qn tdis 18 45 ns OE to Qn; see Fig. 10; VCC = 4.5 V 7
transition time tt 5 18 ns Qn; see Fig. 8 and Fig. 9; VCC = 4.5 V 7
pulse width LE HIGH tW 24 4 ns LE HIGH; VCC = 4.5 V; see Fig. 9 8
set-up time Dn to LE tsu 18 6 ns Dn to LE; VCC = 4.5 V; see Fig. 11 8
hold time Dn to LE th 4 -1 ns Dn to LE; VCC = 4.5 V; see Fig. 11 8
propagation delay Dn to Qn tpd 14 ns Dn to Qn; see Fig. 8; VCC = 5 V; CL = 15 pF 7
propagation delay LE to Qn tpd 13 ns LE to Qn; see Fig. 9; VCC = 5 V; CL = 15 pF 7
power dissipation capacitance per latch CPD 41 pF per latch; VI = GND to (VCC - 1.5 V) 8

CAD (KiCad official)

  • Symbol: 74HCT373PW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74hct373pw-etched.step / 74hct373pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct373pw.step / 74hct373pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 694e57b88d55eac3, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF