component

74HCT30PW-Q100J

Public Made by Adom

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Nexperia Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic ics74hct30pw-q100jfactory-2.0.0extractor-text

Verified 74HCT30PW-Q100J

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: 74HCT30PW-Q100J · TSSOP-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 13-page datasheet
  • ✓distributor: lcsc C547588, digikey 1727-74HCT30PW-Q100JTR-ND, mouser 771-74HCT30PWQ100J
  • ✓family: TSSOP-14_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-a53xuov9/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.10)
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ 74hct30pw-q100j.kicad_sym✓ 74hct30pw-q100j.kicad_mod✓ 74hct30pw-q100j.step
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Ray Publish 0.1.0 de78c0a 1d ago

74HCT30PW-Q100J

Nexperia · Gates · TSSOP-14

74HCT30PW-Q100J from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Data input A of the 8-input NAND gate; inputs include clamp diodes and 74HCT30 uses TTL input levels (VIH min 2.0 V, VIL max 0.8 V).
2 B input Data input B of the 8-input NAND gate.
3 C input Data input C of the 8-input NAND gate.
4 D input Data input D of the 8-input NAND gate.
5 E input Data input E of the 8-input NAND gate.
6 F input Data input F of the 8-input NAND gate.
7 GND power_in Ground (0 V).
8 Y output Data output, goes LOW only when all eight inputs are HIGH.
9 n.c. unconnected Not connected.
10 n.c. unconnected Not connected.
11 G input Data input G of the 8-input NAND gate.
12 H input Data input H of the 8-input NAND gate.
13 n.c. unconnected Not connected.
14 VCC power_in Supply voltage; 4.5 V to 5.5 V recommended for 74HCT30-Q100 (absolute max +7 V).

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 4
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 4
supply current ICC 50 mA 4
ground current IGND -50 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW 4
supply voltage VCC 4.5 5 5.5 V 74HCT30-Q100 4
input voltage VI 0 V max is VCC 4
output voltage VO 0 V max is VCC 4
ambient temperature Tamb -40 125 °C 4
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
HIGH-level input voltage VIH 2 1.6 V VCC = 4.5 V to 5.5 V; 25 °C 6
HIGH-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 6
LOW-level input voltage VIL 1.2 0.8 V VCC = 4.5 V to 5.5 V; 25 °C 6
LOW-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 6
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; 25 °C 6
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; -40 °C to +85 °C 6
HIGH-level output voltage VOH 3.98 4.32 V VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; 25 °C 6
HIGH-level output voltage VOH 3.84 V VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; -40 °C to +85 °C 6
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; -40 °C to +125 °C 6
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; 25 °C 6
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; -40 °C to +85 °C 6
LOW-level output voltage VOL 0.15 0.26 V VI = VIH or VIL; VCC = 4.5 V; IO = 4.0 mA; 25 °C 6
LOW-level output voltage VOL 0.33 V VI = VIH or VIL; VCC = 4.5 V; IO = 4.0 mA; -40 °C to +85 °C 6
LOW-level output voltage VOL 0.4 V VI = VIH or VIL; VCC = 4.5 V; IO = 4.0 mA; -40 °C to +125 °C 6
input leakage current II -0.1 0.1 μA VI = VCC or GND; VCC = 5.5 V; 25 °C 6
input leakage current II -1 1 μA VI = VCC or GND; VCC = 5.5 V; -40 °C to +85 °C 6
supply current ICC 2 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C 6
supply current ICC 20 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +85 °C 6
supply current ICC 40 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C 6
additional supply current ΔICC 60 216 μA per input pin; VI = VCC - 2.4 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; 25 °C 6
additional supply current ΔICC 275 μA per input pin; VI = VCC - 2.4 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 6
additional supply current ΔICC 294 μA per input pin; VI = VCC - 2.4 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 6
propagation delay tpd 16 28 ns A, B, C, D, E, F, G, H to Y; VCC = 4.5 V; CL = 50 pF; 25 °C 7
propagation delay tpd 35 ns A, B, C, D, E, F, G, H to Y; VCC = 4.5 V; CL = 50 pF; -40 °C to +85 °C 7
propagation delay tpd 42 ns A, B, C, D, E, F, G, H to Y; VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C 7
transition time tt 7 15 ns VCC = 4.5 V; CL = 50 pF; 25 °C 7
transition time tt 19 ns VCC = 4.5 V; CL = 50 pF; -40 °C to +85 °C 7
transition time tt 22 ns VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C 7
input capacitance CI 3.5 pF 25 °C 6
propagation delay tpd 12 ns VCC = 5.0 V; CL = 15 pF; 25 °C 7
power dissipation capacitance CPD 15 pF per package; VI = GND to VCC - 1.5 V; 25 °C 7

CAD (KiCad official)

  • Symbol: 74HCT30PW-Q100J
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74hct30pw-q100j-etched.step / 74hct30pw-q100j-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct30pw-q100j.step / 74hct30pw-q100j.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (13 pp, sha256 73ce360c3809095f, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF