# 74HCT273PW

**Nexperia** · Flip Flops · TSSOP-20

74HCT273PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Master reset input (active LOW); a LOW forces all outputs Qn LOW independently of the clock and data inputs. |
| 2 | Q0 | output | Flip-flop 0 output; takes the state of D0 on the LOW-to-HIGH clock transition and is forced LOW while MR is LOW. |
| 3 | D0 | input | Data input for flip-flop 0; must meet set-up and hold times around the LOW-to-HIGH clock transition, and the inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 4 | D1 | input | Data input for flip-flop 1; must meet set-up and hold times around the LOW-to-HIGH clock transition, and the inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 5 | Q1 | output | Flip-flop 1 output; takes the state of D1 on the LOW-to-HIGH clock transition and is forced LOW while MR is LOW. |
| 6 | Q2 | output | Flip-flop 2 output; takes the state of D2 on the LOW-to-HIGH clock transition and is forced LOW while MR is LOW. |
| 7 | D2 | input | Data input for flip-flop 2; must meet set-up and hold times around the LOW-to-HIGH clock transition, and the inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 8 | D3 | input | Data input for flip-flop 3; must meet set-up and hold times around the LOW-to-HIGH clock transition, and the inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 9 | Q3 | output | Flip-flop 3 output; takes the state of D3 on the LOW-to-HIGH clock transition and is forced LOW while MR is LOW. |
| 10 | GND | power_in | Ground (0 V) reference for all voltages. |
| 11 | CP | input | Clock input; edge-triggered on the LOW-to-HIGH transition, at which the Qn outputs take the states of their Dn inputs. |
| 12 | Q4 | output | Flip-flop 4 output; takes the state of D4 on the LOW-to-HIGH clock transition and is forced LOW while MR is LOW. |
| 13 | D4 | input | Data input for flip-flop 4; must meet set-up and hold times around the LOW-to-HIGH clock transition, and the inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 14 | D5 | input | Data input for flip-flop 5; must meet set-up and hold times around the LOW-to-HIGH clock transition, and the inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 15 | Q5 | output | Flip-flop 5 output; takes the state of D5 on the LOW-to-HIGH clock transition and is forced LOW while MR is LOW. |
| 16 | Q6 | output | Flip-flop 6 output; takes the state of D6 on the LOW-to-HIGH clock transition and is forced LOW while MR is LOW. |
| 17 | D6 | input | Data input for flip-flop 6; must meet set-up and hold times around the LOW-to-HIGH clock transition, and the inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 18 | D7 | input | Data input for flip-flop 7; must meet set-up and hold times around the LOW-to-HIGH clock transition, and the inputs include clamp diodes so current-limiting resistors can be used for voltages above VCC. |
| 19 | Q7 | output | Flip-flop 7 output; takes the state of D7 on the LOW-to-HIGH clock transition and is forced LOW while MR is LOW. |
| 20 | VCC | power_in | Supply voltage: 2.0 V to 6.0 V for 74HC273 and 4.5 V to 5.5 V for 74HCT273 (recommended operating conditions). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | 4.5 | 5 | 5.5 | V |  | 4 |
| input voltage | VI | 0 |  |  | V |  | 4 |
| output voltage | VO | 0 |  |  | V |  | 4 |
| ambient temperature | Tamb | -40 |  | 125 | °C |  | 4 |
| input transition rise and fall rate | Δt/ΔV |  | 1.67 | 139 | ns/V | VCC = 4.5 V | 4 |
| supply voltage | VCC | -0.5 |  | 7 | V |  | 4 |
| input clamping current | IIK | -20 |  | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| output clamping current | IOK | -20 |  | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 |
| output current | IO | -25 |  | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 4 |
| supply current | ICC |  |  | 50 | mA |  | 4 |
| ground current | IGND | -50 |  |  | mA |  | 4 |
| storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| total power dissipation | Ptot |  |  | 500 | mW | Tamb = -40 °C to +125 °C | 4 |
| HIGH-level input voltage | VIH | 2 | 1.6 |  | V | VCC = 4.5 V to 5.5 V; 25 °C | 6 |
| HIGH-level input voltage | VIH | 2 |  |  | V | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 |
| LOW-level input voltage | VIL |  | 1.2 | 0.8 | V | VCC = 4.5 V to 5.5 V; 25 °C | 6 |
| LOW-level input voltage | VIL |  |  | 0.8 | V | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 |  | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; 25 °C | 6 |
| HIGH-level output voltage | VOH | 4.4 |  |  | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; -40 °C to +125 °C | 6 |
| HIGH-level output voltage | VOH | 3.98 | 4.32 |  | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; 25 °C | 6 |
| HIGH-level output voltage | VOH | 3.7 |  |  | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; -40 °C to +125 °C | 6 |
| LOW-level output voltage | VOL |  | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; 25 °C | 6 |
| LOW-level output voltage | VOL |  |  | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; -40 °C to +125 °C | 6 |
| LOW-level output voltage | VOL |  | 0.15 | 0.26 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 5.5 V; 25 °C | 6 |
| LOW-level output voltage | VOL |  |  | 0.4 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 5.5 V; -40 °C to +125 °C | 6 |
| input leakage current | II | -0.1 |  | 0.1 | μA | VI = VCC or GND; VCC = 5.5 V; 25 °C | 6 |
| input leakage current | II | -1 |  | 1 | μA | VI = VCC or GND; VCC = 5.5 V; -40 °C to +125 °C | 6 |
| supply current | ICC |  |  | 8 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C | 6 |
| supply current | ICC |  |  | 160 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C | 6 |
| additional supply current, MR input | ΔICC |  | 100 | 360 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; 25 °C | 6 |
| additional supply current, MR input | ΔICC |  |  | 490 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 |
| additional supply current, CP input | ΔICC |  | 175 | 630 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; 25 °C | 6 |
| additional supply current, CP input | ΔICC |  |  | 857.5 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 |
| additional supply current, Dn input | ΔICC |  | 15 | 54 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; 25 °C | 6 |
| additional supply current, Dn input | ΔICC |  |  | 73.5 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 6 |
| propagation delay CP to Qn | tpd |  | 16 | 30 | ns | CP to Qn; VCC = 4.5 V; CL = 50 pF; see Fig. 7; 25 °C | 8 |
| propagation delay CP to Qn | tpd |  |  | 45 | ns | CP to Qn; VCC = 4.5 V; CL = 50 pF; see Fig. 7; -40 °C to +125 °C | 8 |
| HIGH to LOW propagation delay MR to Qn | tPHL |  | 23 | 34 | ns | MR to Qn; VCC = 4.5 V; CL = 50 pF; see Fig. 8; 25 °C | 8 |
| HIGH to LOW propagation delay MR to Qn | tPHL |  |  | 51 | ns | MR to Qn; VCC = 4.5 V; CL = 50 pF; see Fig. 8; -40 °C to +125 °C | 8 |
| transition time | tt |  | 7 | 15 | ns | Qn output; VCC = 4.5 V; see Fig. 7; 25 °C | 8 |
| transition time | tt |  |  | 22 | ns | Qn output; VCC = 4.5 V; see Fig. 7; -40 °C to +125 °C | 8 |
| pulse width CP | tW | 16 | 9 |  | ns | CP input HIGH or LOW; VCC = 4.5 V; see Fig. 7; 25 °C | 8 |
| pulse width CP | tW | 24 |  |  | ns | CP input HIGH or LOW; VCC = 4.5 V; see Fig. 7; -40 °C to +125 °C | 8 |
| pulse width MR | tW | 16 | 8 |  | ns | MR input LOW; VCC = 4.5 V; see Fig. 8; 25 °C | 8 |
| pulse width MR | tW | 24 |  |  | ns | MR input LOW; VCC = 4.5 V; see Fig. 8; -40 °C to +125 °C | 8 |
| recovery time MR to CP | trec | 10 | -2 |  | ns | MR to CP; VCC = 4.5 V; see Fig. 8; 25 °C | 8 |
| recovery time MR to CP | trec | 15 |  |  | ns | MR to CP; VCC = 4.5 V; see Fig. 8; -40 °C to +125 °C | 8 |
| set-up time Dn to CP | tsu | 12 | 5 |  | ns | Dn to CP; VCC = 4.5 V; see Fig. 9; 25 °C | 8 |
| set-up time Dn to CP | tsu | 18 |  |  | ns | Dn to CP; VCC = 4.5 V; see Fig. 9; -40 °C to +125 °C | 8 |
| hold time Dn to CP | th | 3 | -4 |  | ns | Dn to CP; VCC = 4.5 V; see Fig. 9; 25 °C | 8 |
| hold time Dn to CP | th | 3 |  |  | ns | Dn to CP; VCC = 4.5 V; see Fig. 9; -40 °C to +125 °C | 8 |
| maximum frequency | fmax | 30 | 56 |  | MHz | CP input; VCC = 4.5 V; see Fig. 7; 25 °C | 8 |
| maximum frequency | fmax | 20 |  |  | MHz | CP input; VCC = 4.5 V; see Fig. 7; -40 °C to +125 °C | 8 |

## CAD (KiCad official)

- Symbol: `74HCT273PW`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `74hct273pw-etched.step` / `74hct273pw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hct273pw.step` / `74hct273pw.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908449267007488) (17 pp, sha256 `dac5acf608742f73`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74hct273pw-datasheet.pdf)