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74HCT273D

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Nexperia Flip Flops, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HCT273D

Nexperia · Flip Flops · SOIC-20-300mil

74HCT273D from Nexperia, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Master reset input, active LOW; a LOW forces all outputs Qn LOW independently of the clock and data inputs.
2 Q0 output Flip-flop output 0, which takes the state of D0 on a LOW-to-HIGH clock transition and is forced LOW by a LOW on MR.
3 D0 input Data input 0, which must meet the set-up and hold time requirements around the LOW-to-HIGH clock transition on CP.
4 D1 input Data input 1, which must meet the set-up and hold time requirements around the LOW-to-HIGH clock transition on CP.
5 Q1 output Flip-flop output 1, which takes the state of D1 on a LOW-to-HIGH clock transition and is forced LOW by a LOW on MR.
6 Q2 output Flip-flop output 2, which takes the state of D2 on a LOW-to-HIGH clock transition and is forced LOW by a LOW on MR.
7 D2 input Data input 2, which must meet the set-up and hold time requirements around the LOW-to-HIGH clock transition on CP.
8 D3 input Data input 3, which must meet the set-up and hold time requirements around the LOW-to-HIGH clock transition on CP.
9 Q3 output Flip-flop output 3, which takes the state of D3 on a LOW-to-HIGH clock transition and is forced LOW by a LOW on MR.
10 GND power_in Ground (0 V) reference for all voltages.
11 CP input Clock input, edge-triggered on the LOW-to-HIGH transition; common clock for all eight flip-flops.
12 Q4 output Flip-flop output 4, which takes the state of D4 on a LOW-to-HIGH clock transition and is forced LOW by a LOW on MR.
13 D4 input Data input 4, which must meet the set-up and hold time requirements around the LOW-to-HIGH clock transition on CP.
14 D5 input Data input 5, which must meet the set-up and hold time requirements around the LOW-to-HIGH clock transition on CP.
15 Q5 output Flip-flop output 5, which takes the state of D5 on a LOW-to-HIGH clock transition and is forced LOW by a LOW on MR.
16 Q6 output Flip-flop output 6, which takes the state of D6 on a LOW-to-HIGH clock transition and is forced LOW by a LOW on MR.
17 D6 input Data input 6, which must meet the set-up and hold time requirements around the LOW-to-HIGH clock transition on CP.
18 D7 input Data input 7, which must meet the set-up and hold time requirements around the LOW-to-HIGH clock transition on CP.
19 Q7 output Flip-flop output 7, which takes the state of D7 on a LOW-to-HIGH clock transition and is forced LOW by a LOW on MR.
20 VCC power_in Supply voltage: 2.0 V to 6.0 V for 74HC273 and 4.5 V to 5.5 V for 74HCT273 per the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-20-300mil
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC supply voltage VCC 4.5 5 5.5 V 4
input voltage VI 0 V 4
output voltage VO 0 V 4
ambient temperature Tamb -40 125 °C 4
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
supply voltage VCC -0.5 7 V 4
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V [1] 4
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V [1] 4
output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 4
supply current ICC 50 mA 4
ground current IGND -50 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C [2] 4
HIGH-level input voltage VIH 2 1.6 V VCC = 4.5 V to 5.5 V; min at -40 °C to +125 °C 6
LOW-level input voltage VIL 1.2 0.8 V VCC = 4.5 V to 5.5 V; max at -40 °C to +125 °C 6
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; min at -40 °C to +125 °C 6
HIGH-level output voltage VOH 3.7 4.32 V VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; min at -40 °C to +125 °C 6
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; max at -40 °C to +125 °C 6
LOW-level output voltage VOL 0.15 0.4 V VI = VIH or VIL; IO = 5.2 mA; VCC = 5.5 V; max at -40 °C to +125 °C 6
input leakage current II -1 1 μA VI = VCC or GND; VCC = 5.5 V; limits at -40 °C to +125 °C 6
supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; max at -40 °C to +125 °C 6
additional supply current, MR input ΔICC 100 490 μA per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; MR input; max at -40 °C to +125 °C 6
additional supply current, CP input ΔICC 175 857.5 μA per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; CP input; max at -40 °C to +125 °C 6
additional supply current, Dn input ΔICC 15 73.5 μA per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; Dn input; max at -40 °C to +125 °C 6
propagation delay CP to Qn tpd 16 45 ns CP to Qn; see Fig. 7; CL = 50 pF; VCC = 4.5 V; max at -40 °C to +125 °C 8
HIGH to LOW propagation delay MR to Qn tPHL 23 51 ns MR to Qn; see Fig. 8; CL = 50 pF; VCC = 4.5 V; max at -40 °C to +125 °C 8
transition time tt 7 22 ns Qn output; see Fig. 7; VCC = 4.5 V; max at -40 °C to +125 °C 8
pulse width tW 24 9 ns CP input; see Fig. 7; VCC = 4.5 V; min at -40 °C to +125 °C 8
pulse width tW 24 8 ns MR input LOW; see Fig. 8; VCC = 4.5 V; min at -40 °C to +125 °C 8
recovery time trec 15 -2 ns MR to CP; see Fig. 8; VCC = 4.5 V; min at -40 °C to +125 °C 8
set-up time tsu 18 5 ns Dn to CP; see Fig. 9; VCC = 4.5 V; min at -40 °C to +125 °C 8
hold time th 3 -4 ns Dn to CP; see Fig. 9; VCC = 4.5 V; min at -40 °C to +125 °C 8
maximum frequency fmax 20 56 MHz CP input; see Fig. 7; VCC = 4.5 V; min at -40 °C to +125 °C 8

CAD (KiCad official)

  • Symbol: 74HCT273D
  • Footprint: Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm
  • 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
  • 3D model files: 74hct273d-etched.step / 74hct273d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct273d.step / 74hct273d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (17 pp, sha256 dac5acf608742f73, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF