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74HCT164D

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Nexperia Shift Registers, SO-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HCT164D

Nexperia · Shift Registers · SO-14

74HCT164D from Nexperia, in a SO-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DSA input Serial data input DSA; either DSA or DSB can be used as an active HIGH enable for data entry through the other input.
2 DSB input Serial data input DSB; either DSB or DSA can be used as an active HIGH enable for data entry through the other input.
3 Q0 output Parallel data output Q0; forced LOW by an active LOW master reset (MR).
4 Q1 output Parallel data output Q1; forced LOW by an active LOW master reset (MR).
5 Q2 output Parallel data output Q2; forced LOW by an active LOW master reset (MR).
6 Q3 output Parallel data output Q3; forced LOW by an active LOW master reset (MR).
7 GND power_in Ground (0 V) reference for all voltages.
8 CP input Clock input; data is shifted on the LOW-to-HIGH (edge-triggered) transition.
9 MR input Asynchronous master reset input (active LOW); a LOW clears the register and forces all outputs LOW independently of other inputs.
10 Q4 output Parallel data output Q4; forced LOW by an active LOW master reset (MR).
11 Q5 output Parallel data output Q5; forced LOW by an active LOW master reset (MR).
12 Q6 output Parallel data output Q6; forced LOW by an active LOW master reset (MR).
13 Q7 output Parallel data output Q7; forced LOW by an active LOW master reset (MR).
14 VCC power_in Positive supply voltage; the device operates from 2.0 V to 6.0 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SO-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC 4.5 5 5.5 V 74HCT164 4
input voltage VI 0 V 0 to VCC; max printed as VCC 4
output voltage VO 0 V 0 to VCC; max printed as VCC 4
ambient temperature Tamb -40 25 125 °C 4
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
supply voltage VCC -0.5 7 V 4
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 4
supply current ICC 50 mA 4
ground current IGND -50 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW SO14 package; derates 10.1 mW/K above 100 °C 4
HIGH-level input voltage VIH 2 1.6 V VCC = 4.5 V to 5.5 V; 25 °C 5
HIGH-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 5
LOW-level input voltage VIL 1.2 0.8 V VCC = 4.5 V to 5.5 V; 25 °C 5
LOW-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 5
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; 25 °C 5
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +85 °C 5
HIGH-level output voltage VOH 3.98 4.32 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; 25 °C 5
HIGH-level output voltage VOH 3.84 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +85 °C 5
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +125 °C 5
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 4.5 V; 25 °C 5
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 4.5 V; -40 °C to +85 °C 5
LOW-level output voltage VOL 0.15 0.26 V VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; 25 °C 5
LOW-level output voltage VOL 0.33 V VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; -40 °C to +85 °C 5
LOW-level output voltage VOL 0.4 V VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; -40 °C to +125 °C 5
input leakage current II -0.1 0.1 μA VI = VCC or GND; VCC = 6.0 V; 25 °C 5
input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V; -40 °C to +85 °C 5
supply current ICC 8 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; 25 °C 6
supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +85 °C 6
supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C 6
additional supply current per input pin ΔICC 100 360 μA per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; 25 °C 6
additional supply current per input pin ΔICC 450 μA per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 6
additional supply current per input pin ΔICC 490 μA per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 6
propagation delay CP to Qn tpd 17 36 ns CP to Qn; see Fig. 5; VCC = 4.5 V; 25 °C 7
propagation delay CP to Qn tpd 45 ns CP to Qn; see Fig. 5; VCC = 4.5 V; -40 °C to +85 °C 7
propagation delay CP to Qn tpd 54 ns CP to Qn; see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C 7
HIGH to LOW propagation delay MR to Qn tPHL 19 38 ns MR to Qn; see Fig. 6; VCC = 4.5 V; 25 °C 7
HIGH to LOW propagation delay MR to Qn tPHL 48 ns MR to Qn; see Fig. 6; VCC = 4.5 V; -40 °C to +85 °C 7
HIGH to LOW propagation delay MR to Qn tPHL 57 ns MR to Qn; see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C 7
transition time tt 7 15 ns CP HIGH or LOW; see Fig. 5; VCC = 4.5 V; 25 °C 7
transition time tt 19 ns CP HIGH or LOW; see Fig. 5; VCC = 4.5 V; -40 °C to +85 °C 7
transition time tt 22 ns CP HIGH or LOW; see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C 7
pulse width CP tW 18 7 ns CP HIGH or LOW; see Fig. 5; VCC = 4.5 V; 25 °C 7
pulse width CP tW 23 ns CP HIGH or LOW; see Fig. 5; VCC = 4.5 V; -40 °C to +85 °C 7
pulse width CP tW 27 ns CP HIGH or LOW; see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C 7
set-up time DSA and DSB to CP tsu 12 6 ns DSA, and DSB to CP; see Fig. 7; VCC = 4.5 V; 25 °C 7
set-up time DSA and DSB to CP tsu 15 ns DSA, and DSB to CP; see Fig. 7; VCC = 4.5 V; -40 °C to +85 °C 7
set-up time DSA and DSB to CP tsu 18 ns DSA, and DSB to CP; see Fig. 7; VCC = 4.5 V; -40 °C to +125 °C 7
hold time DSA and DSB to CP th 4 -2 ns DSA, and DSB to CP; see Fig. 7; VCC = 4.5 V; 25 °C 7
maximum frequency fmax 27 55 MHz CP; see Fig. 5; VCC = 4.5 V; 25 °C 8
maximum frequency fmax 22 MHz CP; see Fig. 5; VCC = 4.5 V; -40 °C to +85 °C 8
maximum frequency fmax 18 MHz CP; see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C 8

CAD (KiCad official)

  • Symbol: 74HCT164D
  • Footprint: Adom_Gen:Nexperia_74
  • 3D model: SO-14 (KiCad packages3D, STEP)
  • 3D model files: 74hct164d-etched.step / 74hct164d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct164d.step / 74hct164d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (16 pp, sha256 aa299aaeb852d99f, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF