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Contents

README

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74HCT138D

Nexperia · Signal Switches / Encoders & Decoders / Multiplexers · SOIC-16

74HCT138D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Address input bit 0 (LSB). TTL-compatible input; selects one of eight outputs together with A1 and A2.
2 A1 input Address input bit 1. TTL-compatible input; selects one of eight outputs together with A0 and A2.
3 A2 input Address input bit 2 (MSB). TTL-compatible input; selects one of eight outputs together with A0 and A1.
4 E1 input Enable input 1, active LOW. All outputs are HIGH unless E1 and E2 are LOW and E3 is HIGH.
5 E2 input Enable input 2, active LOW. All outputs are HIGH unless E1 and E2 are LOW and E3 is HIGH.
6 E3 input Enable input 3, active HIGH. Must be HIGH (with E1, E2 LOW) to enable the decoder outputs.
7 Y7 output Decoder output 7, active LOW. Driven LOW when A2=A1=A0=HIGH and the chip is enabled; otherwise HIGH.
8 GND power_in Ground reference (0 V).
9 Y6 output Decoder output 6, active LOW. Driven LOW when A2=A1=HIGH, A0=LOW and the chip is enabled; otherwise HIGH.
10 Y5 output Decoder output 5, active LOW. Driven LOW when A2=HIGH, A1=LOW, A0=HIGH and the chip is enabled; otherwise HIGH.
11 Y4 output Decoder output 4, active LOW. Driven LOW when A2=HIGH, A1=A0=LOW and the chip is enabled; otherwise HIGH.
12 Y3 output Decoder output 3, active LOW. Driven LOW when A2=LOW, A1=A0=HIGH and the chip is enabled; otherwise HIGH.
13 Y2 output Decoder output 2, active LOW. Driven LOW when A2=LOW, A1=HIGH, A0=LOW and the chip is enabled; otherwise HIGH.
14 Y1 output Decoder output 1, active LOW. Driven LOW when A2=A1=LOW, A0=HIGH and the chip is enabled; otherwise HIGH.
15 Y0 output Decoder output 0, active LOW. Driven LOW when A2=A1=A0=LOW and the chip is enabled; otherwise HIGH.
16 VCC power_in Positive supply voltage. Recommended operating range 4.5 V to 5.5 V for 74HCT138; absolute maximum -0.5 V to +7 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

Ordering variants

Same part, different packaging or reel option.

  • 74HCT138DD
  • 74HCT138DPW
  • 74HCT138DBQ

CAD (KiCad official)

  • Symbol: 74HCT138D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 74hct138d-etched.step / 74hct138d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct138d.step / 74hct138d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 645120bc441507e9, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF