component
74HCT132D
Public Made by Adomby adom
Nexperia Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HCT132D
Nexperia · Logic Gates · SOIC-14
74HCT132D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of NAND gate 1, a Schmitt-trigger input with clamp diodes; input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V. |
| 2 | 1B | input | Data input 1B of NAND gate 1, a Schmitt-trigger input with clamp diodes; input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V. |
| 3 | 1Y | output | Data output 1Y of NAND gate 1; output current is limited to ±25 mA for -0.5 V < VO < VCC + 0.5 V. |
| 4 | 2A | input | Data input 2A of NAND gate 2, a Schmitt-trigger input with clamp diodes; input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V. |
| 5 | 2B | input | Data input 2B of NAND gate 2, a Schmitt-trigger input with clamp diodes; input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V. |
| 6 | 2Y | output | Data output 2Y of NAND gate 2; output current is limited to ±25 mA for -0.5 V < VO < VCC + 0.5 V. |
| 7 | GND | power_in | Ground (0 V) reference pin; the datasheet gives the supply limits and voltages referenced to this pin. |
| 8 | 3Y | output | Data output 3Y of NAND gate 3; output current is limited to ±25 mA for -0.5 V < VO < VCC + 0.5 V. |
| 9 | 3A | input | Data input 3A of NAND gate 3, a Schmitt-trigger input with clamp diodes; input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V. |
| 10 | 3B | input | Data input 3B of NAND gate 3, a Schmitt-trigger input with clamp diodes; input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V. |
| 11 | 4Y | output | Data output 4Y of NAND gate 4; output current is limited to ±25 mA for -0.5 V < VO < VCC + 0.5 V. |
| 12 | 4A | input | Data input 4A of NAND gate 4, a Schmitt-trigger input with clamp diodes; input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V. |
| 13 | 4B | input | Data input 4B of NAND gate 4, a Schmitt-trigger input with clamp diodes; input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V. |
| 14 | VCC | power_in | Supply voltage; the absolute maximum is -0.5 V to +7 V, with recommended operation at 2.0 V to 6.0 V for 74HC132 and 4.5 V to 5.5 V for 74HCT132. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | 4.5 | 5 | 5.5 | V | 74HCT132 column | 4 |
| input voltage | VI | 0 | V | 4 | |||
| output voltage | VO | 0 | V | 4 | |||
| ambient temperature | Tamb | -40 | 25 | 125 | °C | 74HCT132 column | 4 |
| supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 3 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 3 | |
| output current | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 3 | |
| supply current | ICC | 50 | mA | 3 | |||
| ground current | IGND | -50 | mA | 3 | |||
| storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| total power dissipation | Ptot | 500 | mW | SOT108-1 (SO14); derates linearly 10.1 mW/K above 100 °C | 3 | ||
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VT+ or VT-; VCC = 4.5 V; IO = -20 μA; Tamb = 25 °C | 4 | |
| HIGH-level output voltage | VOH | 4.4 | V | VI = VT+ or VT-; VCC = 4.5 V; IO = -20 μA; Tamb = -40 °C to +85 °C | 4 | ||
| HIGH-level output voltage | VOH | 3.98 | 4.32 | V | VI = VT+ or VT-; VCC = 4.5 V; IO = -4.0 mA; Tamb = 25 °C | 4 | |
| HIGH-level output voltage | VOH | 3.84 | V | VI = VT+ or VT-; VCC = 4.5 V; IO = -4.0 mA; Tamb = -40 °C to +85 °C | 4 | ||
| HIGH-level output voltage | VOH | 3.7 | V | VI = VT+ or VT-; VCC = 4.5 V; IO = -4.0 mA; Tamb = -40 °C to +125 °C | 4 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VT+ or VT-; VCC = 4.5 V; IO = 20 μA; Tamb = 25 °C | 4 | |
| LOW-level output voltage | VOL | 0.1 | V | VI = VT+ or VT-; VCC = 4.5 V; IO = 20 μA; Tamb = -40 °C to +85 °C | 4 | ||
| LOW-level output voltage | VOL | 0.15 | 0.26 | V | VI = VT+ or VT-; VCC = 4.5 V; IO = 4.0 mA; Tamb = 25 °C | 4 | |
| LOW-level output voltage | VOL | 0.33 | V | VI = VT+ or VT-; VCC = 4.5 V; IO = 4.0 mA; Tamb = -40 °C to +85 °C | 4 | ||
| LOW-level output voltage | VOL | 0.4 | V | VI = VT+ or VT-; VCC = 4.5 V; IO = 4.0 mA; Tamb = -40 °C to +125 °C | 4 | ||
| input leakage current | II | -0.1 | 0.1 | μA | VI = VCC or GND; VCC = 5.5 V; Tamb = 25 °C | 5 | |
| input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 5.5 V; Tamb = -40 °C to +85 °C | 5 | |
| supply current | ICC | 2 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = 25 °C | 5 | ||
| supply current | ICC | 20 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = -40 °C to +85 °C | 5 | ||
| supply current | ICC | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = -40 °C to +125 °C | 5 | ||
| additional supply current | ΔICC | 30 | 108 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V; Tamb = 25 °C | 5 | |
| additional supply current | ΔICC | 135 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +85 °C | 5 | ||
| additional supply current | ΔICC | 147 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C | 5 | ||
| propagation delay nA, nB to nY | tpd | 20 | 33 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 4; Tamb = 25 °C | 5 | |
| propagation delay nA, nB to nY | tpd | 41 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 4; Tamb = -40 °C to +85 °C | 5 | ||
| propagation delay nA, nB to nY | tpd | 50 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 4; Tamb = -40 °C to +125 °C | 5 | ||
| transition time | tt | 7 | 15 | ns | VCC = 4.5 V; see Fig. 4; Tamb = 25 °C | 5 | |
| transition time | tt | 19 | ns | VCC = 4.5 V; see Fig. 4; Tamb = -40 °C to +85 °C | 5 | ||
| transition time | tt | 22 | ns | VCC = 4.5 V; see Fig. 4; Tamb = -40 °C to +125 °C | 5 | ||
| positive-going threshold voltage | VT+ | 1.2 | 1.41 | 1.9 | V | VCC = 4.5 V; Tamb = 25 °C | 7 |
| positive-going threshold voltage | VT+ | 1.2 | 1.9 | V | VCC = 4.5 V; Tamb = -40 °C to +85 °C | 7 | |
| positive-going threshold voltage | VT+ | 1.4 | 1.59 | 2.1 | V | VCC = 5.5 V; Tamb = 25 °C | 7 |
| positive-going threshold voltage | VT+ | 1.4 | 2.1 | V | VCC = 5.5 V; Tamb = -40 °C to +85 °C | 7 | |
| negative-going threshold voltage | VT- | 0.5 | 0.85 | 1.2 | V | VCC = 4.5 V; Tamb = 25 °C | 7 |
| negative-going threshold voltage | VT- | 0.5 | 1.2 | V | VCC = 4.5 V; Tamb = -40 °C to +85 °C | 7 | |
| negative-going threshold voltage | VT- | 0.6 | 0.99 | 1.4 | V | VCC = 5.5 V; Tamb = 25 °C | 7 |
| negative-going threshold voltage | VT- | 0.6 | 1.4 | V | VCC = 5.5 V; Tamb = -40 °C to +85 °C | 7 | |
| hysteresis voltage | VH | 0.4 | 0.56 | V | VCC = 4.5 V; Tamb = 25 °C | 7 | |
| hysteresis voltage | VH | 0.4 | V | VCC = 4.5 V; Tamb = -40 °C to +85 °C | 7 | ||
| hysteresis voltage | VH | 0.4 | 0.6 | V | VCC = 5.5 V; Tamb = 25 °C | 7 |
CAD (KiCad official)
- Symbol:
74HCT132D - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
74hct132d-etched.step/74hct132d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hct132d.step/74hct132d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (16 pp, sha256
f76ea712a3e4707e, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).