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docs 74hct125d: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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74hct125d-etched.fit.json 74hct125d: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74hct125d-etched.glb 74hct125d: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74hct125d-etched.step 74hct125d: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
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page.json 74hct125d: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 28d ago
README.md 74hct125d: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

74HCT125D

Nexperia · Buffers, Drivers, Receivers, Transceivers · SOIC-14

74HCT125D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1OE input Output enable input for buffer 1 (active LOW). LOW enables 1Y to follow 1A; HIGH puts 1Y in high-impedance OFF-state. TTL input levels (VIH min 2.0 V, VIL max 0.8 V at VCC = 4.5-5.5 V).
2 1A input Data input for buffer 1. Passed through to 1Y when 1OE is LOW. TTL input levels; input leakage ±0.1 µA typ, input capacitance 3.5 pF typ.
3 1Y tri_state Data output for buffer 1. Drives the value of 1A when 1OE is LOW; high-impedance when 1OE is HIGH. Rated for IO up to ±35 mA absolute max; VOH ≥ 3.98 V at IO = -6 mA, VOL ≤ 0.26 V at IO = 6 mA (VCC = 4.5 V).
4 2OE input Output enable input for buffer 2 (active LOW). LOW enables 2Y to follow 2A; HIGH puts 2Y in high-impedance OFF-state.
5 2A input Data input for buffer 2. Passed through to 2Y when 2OE is LOW.
6 2Y tri_state Data output for buffer 2. Drives the value of 2A when 2OE is LOW; high-impedance when 2OE is HIGH.
7 GND power_in Ground reference (0 V). Maximum sustained ground current ±70 mA per absolute maximum ratings.
8 3Y tri_state Data output for buffer 3. Drives the value of 3A when 3OE is LOW; high-impedance when 3OE is HIGH.
9 3A input Data input for buffer 3. Passed through to 3Y when 3OE is LOW.
10 3OE input Output enable input for buffer 3 (active LOW). LOW enables 3Y to follow 3A; HIGH puts 3Y in high-impedance OFF-state.
11 4Y tri_state Data output for buffer 4. Drives the value of 4A when 4OE is LOW; high-impedance when 4OE is HIGH.
12 4A input Data input for buffer 4. Passed through to 4Y when 4OE is LOW.
13 4OE input Output enable input for buffer 4 (active LOW). LOW enables 4Y to follow 4A; HIGH puts 4Y in high-impedance OFF-state.
14 VCC power_in Positive supply voltage. Recommended 4.5 V to 5.5 V for 74HCT125; absolute maximum -0.5 V to +7 V. Supply current ICC ≤ 8 µA at 25 °C (VCC = 5.5 V).

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • 74HCT125DD
  • 74HCT125DPW

CAD (KiCad official)

  • Symbol: 74HCT125D
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: 74hct125d-etched.step / 74hct125d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct125d.step / 74hct125d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (13 pp, sha256 3b5da3a3dcae2624, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF