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74HCT11PW-Q100J

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Nexperia Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HCT11PW-Q100J

Nexperia · Logic Gates · TSSOP-14

74HCT11PW-Q100J from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Data input 1A of gate 1; input voltage range is 0 V to VCC, and input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V.
2 1B input Data input 1B of gate 1; input voltage range is 0 V to VCC, and input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V.
3 2A input Data input 2A of gate 2; input voltage range is 0 V to VCC, and input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V.
4 2B input Data input 2B of gate 2; input voltage range is 0 V to VCC, and input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V.
5 2C input Data input 2C of gate 2; input voltage range is 0 V to VCC, and input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V.
6 2Y output Data output 2Y of gate 2; output current is limited to ±25 mA for -0.5 V < VO < VCC + 0.5 V.
7 GND power_in Ground (0 V) reference for all voltages; ground current is limited to -50 mA.
8 3Y output Data output 3Y of gate 3; output current is limited to ±25 mA for -0.5 V < VO < VCC + 0.5 V.
9 3A input Data input 3A of gate 3; input voltage range is 0 V to VCC, and input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V.
10 3B input Data input 3B of gate 3; input voltage range is 0 V to VCC, and input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V.
11 3C input Data input 3C of gate 3; input voltage range is 0 V to VCC, and input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V.
12 1Y output Data output 1Y of gate 1; output current is limited to ±25 mA for -0.5 V < VO < VCC + 0.5 V.
13 1C input Data input 1C of gate 1; input voltage range is 0 V to VCC, and input clamping current is limited to ±20 mA when VI < -0.5 V or VI > VCC + 0.5 V.
14 VCC power_in Supply voltage; recommended range is 2.0 V to 6.0 V for 74HC11-Q100 and 4.5 V to 5.5 V for 74HCT11-Q100, with absolute maximum -0.5 V to +7 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VCC -0.5 7 V Voltages referenced to GND 3
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V; see note [1] 3
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V; see note [1] 3
Output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 3
Supply current (absolute maximum) ICC 50 mA 3
Ground current IGND -50 mA 3
Storage temperature Tstg -65 150 °C 3
Total power dissipation Ptot 500 mW note [2]: TSSOP14 (SOT402-1) derates linearly 7.3 mW/K above 81 °C 3
Supply voltage VCC 4.5 5 5.5 V 74HCT11-Q100 column 3
Input voltage VI 0 V max printed as VCC 3
Output voltage VO 0 V max printed as VCC 3
Ambient temperature Tamb -40 125 °C 3
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 3
HIGH-level input voltage VIH 2 1.6 V VCC = 4.5 V to 5.5 V; 25 °C 4
HIGH-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 4
LOW-level input voltage VIL 1.2 0.8 V VCC = 4.5 V to 5.5 V; 25 °C 4
LOW-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 4
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; 25 °C 4
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +85 °C 4
HIGH-level output voltage VOH 3.98 4.32 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; 25 °C 4
HIGH-level output voltage VOH 3.84 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +85 °C 4
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +125 °C 4
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 4.5 V; 25 °C 4
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 4.5 V; -40 °C to +85 °C 4
Input leakage current II -0.1 0.1 μA VI = VCC or GND; VCC = 5.5 V; 25 °C 4
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 5.5 V; -40 °C to +85 °C 4
Supply current ICC 2 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C 4
Supply current ICC 20 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +85 °C 4
Supply current ICC 40 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C 4
Additional supply current per input pin ΔICC 100 360 μA per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; 25 °C 5
Additional supply current per input pin ΔICC 450 μA per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +85 °C 5
Additional supply current per input pin ΔICC 490 μA per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C 5
Propagation delay nA, nB to nY tpd 16 24 ns VCC = 4.5 V; CL = 50 pF; see Fig. 4; 25 °C 5
Propagation delay nA, nB to nY tpd 30 ns VCC = 4.5 V; CL = 50 pF; see Fig. 4; -40 °C to +85 °C 5
Propagation delay nA, nB to nY tpd 36 ns VCC = 4.5 V; CL = 50 pF; see Fig. 4; -40 °C to +125 °C 5
Transition time tt 7 15 ns VCC = 4.5 V; CL = 50 pF; see Fig. 4; 25 °C 5
Transition time tt 19 ns VCC = 4.5 V; CL = 50 pF; see Fig. 4; -40 °C to +85 °C 5
Transition time tt 22 ns VCC = 4.5 V; CL = 50 pF; see Fig. 4; -40 °C to +125 °C 5

CAD (KiCad official)

  • Symbol: 74HCT11PW-Q100J
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74hct11pw-q100j-etched.step / 74hct11pw-q100j-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct11pw-q100j.step / 74hct11pw-q100j.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (11 pp, sha256 e3b0aa8fa9d1c505, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF