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74HCT109D

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Nexperia Flip Flops, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HCT109D

Nexperia · Flip Flops · SOP-16

74HCT109D from Nexperia, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1RD input Asynchronous reset input for flip-flop 1, active LOW, operating independently of the clock input.
2 1J input Synchronous J input for flip-flop 1, which must be stable one set-up time before the LOW-to-HIGH clock transition for predictable operation.
3 1K input Synchronous K input for flip-flop 1, which must be stable one set-up time before the LOW-to-HIGH clock transition for predictable operation.
4 1CP input Clock input for flip-flop 1, edge-triggered on the LOW-to-HIGH transition, with Schmitt-trigger action that tolerates slower clock rise and fall times.
5 1SD input Asynchronous set input for flip-flop 1, active LOW, operating independently of the clock input.
6 1Q output True flip-flop output for flip-flop 1.
7 1Q̄ output Complement flip-flop output for flip-flop 1.
8 GND power_in Ground reference, 0 V; all voltages are referenced to GND.
9 2Q̄ output Complement flip-flop output for flip-flop 2.
10 2Q output True flip-flop output for flip-flop 2.
11 2SD input Asynchronous set input for flip-flop 2, active LOW, operating independently of the clock input.
12 2CP input Clock input for flip-flop 2, edge-triggered on the LOW-to-HIGH transition, with Schmitt-trigger action that tolerates slower clock rise and fall times.
13 2K input Synchronous K input for flip-flop 2, which must be stable one set-up time before the LOW-to-HIGH clock transition for predictable operation.
14 2J input Synchronous J input for flip-flop 2, which must be stable one set-up time before the LOW-to-HIGH clock transition for predictable operation.
15 2RD input Asynchronous reset input for flip-flop 2, active LOW, operating independently of the clock input.
16 VCC power_in Supply voltage: 2.0 V to 6.0 V for 74HC109 and 4.5 V to 5.5 V for 74HCT109 under recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage VI 0 V 4
Output voltage VO 0 V 4
Supply voltage VCC 4.5 5 5.5 V 74HCT109 4
Ambient temperature Tamb -40 25 125 °C 4
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
Supply voltage VCC -0.5 7 V 3
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 3
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 3
Output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 3
Supply current ICC 50 mA 3
Ground current IGND -50 mA 3
Storage temperature Tstg -65 150 °C 3
Total power dissipation Ptot 500 mW see note [1]: SO16 (SOT109-1) derates 12.4 mW/K above 110 °C 3
HIGH-level input voltage VIH 2 1.6 V VCC = 4.5 V to 5.5 V; Tamb = 25 °C 5
HIGH-level input voltage VIH 2 V VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C 5
LOW-level input voltage VIL 1.2 0.8 V VCC = 4.5 V to 5.5 V; Tamb = 25 °C 5
LOW-level input voltage VIL 0.8 V VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C 5
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; Tamb = 25 °C 5
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; Tamb = -40 °C to +125 °C 5
HIGH-level output voltage VOH 3.98 4.32 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; Tamb = 25 °C 5
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; Tamb = -40 °C to +125 °C 5
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 4.5 V; Tamb = 25 °C 5
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 4.5 V; Tamb = -40 °C to +125 °C 5
LOW-level output voltage VOL 0.15 0.26 V IO = 5.2 mA; VCC = 5.5 V; Tamb = 25 °C 5
LOW-level output voltage VOL 0.4 V IO = 5.2 mA; VCC = 5.5 V; Tamb = -40 °C to +125 °C 5
Input leakage current II -0.1 0.1 μA VI = VCC or GND; VCC = 5.5 V; Tamb = 25 °C 5
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 5.5 V; Tamb = -40 °C to +125 °C 5
Supply current ICC 4 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = 25 °C 5
Supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 5.5 V; Tamb = -40 °C to +125 °C 5
Additional supply current ΔICC 35 126 μA per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; Tamb = 25 °C 5
Additional supply current ΔICC 171.5 μA per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; Tamb = -40 °C to +125 °C 5
Propagation delay nCP to nQ, nQ tpd 20 35 ns VCC = 4.5 V; CL = 50 pF; see Fig. 4; Tamb = 25 °C 7
Propagation delay nCP to nQ, nQ tpd 53 ns VCC = 4.5 V; CL = 50 pF; see Fig. 4; Tamb = -40 °C to +125 °C 7
LOW-to-HIGH propagation delay nSD to nQ tPLH 13 26 ns VCC = 4.5 V; CL = 50 pF; see Fig. 5; Tamb = 25 °C 7
LOW-to-HIGH propagation delay nSD to nQ tPLH 39 ns VCC = 4.5 V; CL = 50 pF; see Fig. 5; Tamb = -40 °C to +125 °C 7
HIGH-to-LOW propagation delay nSD to nQ tPHL 19 35 ns VCC = 4.5 V; CL = 50 pF; see Fig. 5; Tamb = 25 °C 7
HIGH-to-LOW propagation delay nSD to nQ tPHL 53 ns VCC = 4.5 V; CL = 50 pF; see Fig. 5; Tamb = -40 °C to +125 °C 7
HIGH-to-LOW propagation delay nRD to nQ tPHL 19 35 ns VCC = 4.5 V; CL = 50 pF; see Fig. 5; Tamb = 25 °C 7
HIGH-to-LOW propagation delay nRD to nQ tPHL 53 ns VCC = 4.5 V; CL = 50 pF; see Fig. 5; Tamb = -40 °C to +125 °C 7
LOW-to-HIGH propagation delay nRD to nQ tPLH 16 32 ns VCC = 4.5 V; CL = 50 pF; see Fig. 5; Tamb = 25 °C 7
LOW-to-HIGH propagation delay nRD to nQ tPLH 48 ns VCC = 4.5 V; CL = 50 pF; see Fig. 5; Tamb = -40 °C to +125 °C 7
Transition time tt 7 15 ns nQ, nQ; VCC = 4.5 V; see Fig. 4; Tamb = 25 °C 7
Transition time tt 22 ns nQ, nQ; VCC = 4.5 V; see Fig. 4; Tamb = -40 °C to +125 °C 7
Pulse width nCP HIGH or LOW tW 18 9 ns VCC = 4.5 V; see Fig. 4; Tamb = 25 °C 7
Pulse width nCP HIGH or LOW tW 27 ns VCC = 4.5 V; see Fig. 4; Tamb = -40 °C to +125 °C 7
Pulse width nSD, nRD HIGH or LOW tW 16 8 ns VCC = 4.5 V; see Fig. 5; Tamb = 25 °C 7
Pulse width nSD, nRD HIGH or LOW tW 24 ns VCC = 4.5 V; see Fig. 5; Tamb = -40 °C to +125 °C 7
Recovery time nSD, nRD to nCP trec 16 8 ns VCC = 4.5 V; see Fig. 5; Tamb = 25 °C 7
Recovery time nSD, nRD to nCP trec 24 ns VCC = 4.5 V; see Fig. 5; Tamb = -40 °C to +125 °C 7
Set-up time nJ and nK to nCP tsu 18 8 ns VCC = 4.5 V; see Fig. 4; Tamb = 25 °C 8
Set-up time nJ and nK to nCP tsu 27 ns VCC = 4.5 V; see Fig. 4; Tamb = -40 °C to +125 °C 8
Hold time nJ and nK to nCP th 3 -3 ns VCC = 4.5 V; see Fig. 4; Tamb = 25 °C 8
Hold time nJ and nK to nCP th 3 ns VCC = 4.5 V; see Fig. 4; Tamb = -40 °C to +125 °C 8
Maximum frequency nCP fmax 27 55 MHz VCC = 4.5 V; see Fig. 4; Tamb = 25 °C 8
Maximum frequency nCP fmax 18 MHz VCC = 4.5 V; see Fig. 4; Tamb = -40 °C to +125 °C 8

CAD (KiCad official)

  • Symbol: 74HCT109D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74hct109d-etched.step / 74hct109d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hct109d.step / 74hct109d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 55aafe72390e1fbc, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF