component
74HCT00PW
Public Made by Adomby adom
Nexperia Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74HCT00PW
Nexperia · Logic Gates · TSSOP-14
74HCT00PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of gate 1; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 2 | 1B | input | Data input of gate 1; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 3 | 1Y | output | Data output of gate 1; output current IO is limited to ±25 mA. |
| 4 | 2A | input | Data input of gate 2; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 5 | 2B | input | Data input of gate 2; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 6 | 2Y | output | Data output of gate 2; output current IO is limited to ±25 mA. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 3Y | output | Data output of gate 3; output current IO is limited to ±25 mA. |
| 9 | 3A | input | Data input of gate 3; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 10 | 3B | input | Data input of gate 3; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 11 | 4Y | output | Data output of gate 4; output current IO is limited to ±25 mA. |
| 12 | 4A | input | Data input of gate 4; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 13 | 4B | input | Data input of gate 4; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 14 | VCC | power_in | Supply voltage; 74HCT00 recommended range is 4.5 V to 5.5 V, with absolute maximum of -0.5 V to +7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V [1] | 3 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V [1] | 3 | |
| output current | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 3 | |
| supply current | ICC | 50 | mA | 3 | |||
| ground current | IGND | -50 | mA | 3 | |||
| storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| total power dissipation | Ptot | 500 | mW | [2] For SOT402-1 (TSSOP14): derates linearly with 7.3 mW/K above 81 °C | 3 | ||
| supply voltage | VCC | 4.5 | 5 | 5.5 | V | 74HCT00 | 3 |
| input voltage | VI | 0 | V | 0 to VCC | 3 | ||
| output voltage | VO | 0 | V | 0 to VCC | 3 | ||
| ambient temperature | Tamb | -40 | 25 | 125 | °C | 3 | |
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 3 | |
| HIGH-level input voltage | VIH | 2 | 1.6 | V | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 4 | |
| LOW-level input voltage | VIL | 1.2 | 0.8 | V | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 4 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; -40 °C to +125 °C | 4 | |
| HIGH-level output voltage | VOH | 3.7 | 4.32 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; -40 °C to +125 °C | 4 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; -40 °C to +125 °C | 4 | |
| LOW-level output voltage | VOL | 0.15 | 0.4 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 4 mA; -40 °C to +125 °C | 4 | |
| input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 4 | |
| supply current | ICC | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 4 | ||
| additional supply current | ΔICC | 150 | 735 | μA | per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 5 | |
| propagation delay | tpd | 12 | 29 | ns | nA, nB to nY; see Fig. 4; VCC = 4.5 V; -40 °C to +125 °C | 5 | |
| transition time | tt | 22 | ns | VCC = 4.5 V; see Fig. 4 [2]; -40 °C to +125 °C | 5 |
CAD (KiCad official)
- Symbol:
74HCT00PW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74hct00pw-etched.step/74hct00pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hct00pw.step/74hct00pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
a01759669120aa7d, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74HCT00PW
**Nexperia** · Logic Gates · TSSOP-14
74HCT00PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input of gate 1; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 2 | 1B | input | Data input of gate 1; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 3 | 1Y | output | Data output of gate 1; output current IO is limited to ±25 mA. |
| 4 | 2A | input | Data input of gate 2; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 5 | 2B | input | Data input of gate 2; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 6 | 2Y | output | Data output of gate 2; output current IO is limited to ±25 mA. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 3Y | output | Data output of gate 3; output current IO is limited to ±25 mA. |
| 9 | 3A | input | Data input of gate 3; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 10 | 3B | input | Data input of gate 3; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 11 | 4Y | output | Data output of gate 4; output current IO is limited to ±25 mA. |
| 12 | 4A | input | Data input of gate 4; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 13 | 4B | input | Data input of gate 4; the input has clamp diodes, so current limiting resistors can be used when driving it above VCC, with IIK limited to ±20 mA. |
| 14 | VCC | power_in | Supply voltage; 74HCT00 recommended range is 4.5 V to 5.5 V, with absolute maximum of -0.5 V to +7 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | -0.5 | | 7 | V | | 3 |
| input clamping current | IIK | -20 | | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V [1] | 3 |
| output clamping current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V [1] | 3 |
| output current | IO | -25 | | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 3 |
| supply current | ICC | | | 50 | mA | | 3 |
| ground current | IGND | -50 | | | mA | | 3 |
| storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| total power dissipation | Ptot | | | 500 | mW | [2] For SOT402-1 (TSSOP14): derates linearly with 7.3 mW/K above 81 °C | 3 |
| supply voltage | VCC | 4.5 | 5 | 5.5 | V | 74HCT00 | 3 |
| input voltage | VI | 0 | | | V | 0 to VCC | 3 |
| output voltage | VO | 0 | | | V | 0 to VCC | 3 |
| ambient temperature | Tamb | -40 | 25 | 125 | °C | | 3 |
| input transition rise and fall rate | Δt/ΔV | | 1.67 | 139 | ns/V | VCC = 4.5 V | 3 |
| HIGH-level input voltage | VIH | 2 | 1.6 | | V | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 4 |
| LOW-level input voltage | VIL | | 1.2 | 0.8 | V | VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; -40 °C to +125 °C | 4 |
| HIGH-level output voltage | VOH | 3.7 | 4.32 | | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; -40 °C to +125 °C | 4 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; -40 °C to +125 °C | 4 |
| LOW-level output voltage | VOL | | 0.15 | 0.4 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 4 mA; -40 °C to +125 °C | 4 |
| input leakage current | II | -1 | | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 4 |
| supply current | ICC | | | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 4 |
| additional supply current | ΔICC | | 150 | 735 | μA | per input pin; VI = VCC - 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 5 |
| propagation delay | tpd | | 12 | 29 | ns | nA, nB to nY; see Fig. 4; VCC = 4.5 V; -40 °C to +125 °C | 5 |
| transition time | tt | | | 22 | ns | VCC = 4.5 V; see Fig. 4 [2]; -40 °C to +125 °C | 5 |
## CAD (KiCad official)
- Symbol: `74HCT00PW`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `74hct00pw-etched.step` / `74hct00pw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hct00pw.step` / `74hct00pw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74HCT00PW.pdf) (12 pp, sha256 `a01759669120aa7d`, retrieved 2026-10-17, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74hct00pw-datasheet.pdf)