component
74HC86PW
Public Made by Adomby adom
Nexperia Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74HC86PW
Nexperia · Logic Gates · TSSOP-14
74HC86PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of the first EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 2 | 1B | input | Data input 1B of the first EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 3 | 1Y | output | Data output 1Y of the first EXCLUSIVE-OR gate, which goes HIGH only when inputs 1A and 1B differ. |
| 4 | 2A | input | Data input 2A of the second EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 5 | 2B | input | Data input 2B of the second EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 6 | 2Y | output | Data output 2Y of the second EXCLUSIVE-OR gate, which goes HIGH only when inputs 2A and 2B differ. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 3Y | output | Data output 3Y of the third EXCLUSIVE-OR gate, which goes HIGH only when inputs 3A and 3B differ. |
| 9 | 3A | input | Data input 3A of the third EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 10 | 3B | input | Data input 3B of the third EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 11 | 4Y | output | Data output 4Y of the fourth EXCLUSIVE-OR gate, which goes HIGH only when inputs 4A and 4B differ. |
| 12 | 4A | input | Data input 4A of the fourth EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 13 | 4B | input | Data input 4B of the fourth EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 14 | VCC | power_in | Supply voltage; recommended range is 2.0 V to 6.0 V for 74HC86 and 4.5 V to 5.5 V for 74HCT86. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 2 | 5 | 6 | V | 4 | |
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 4 | |
| Input voltage | VI | 0 | V | 4 | |||
| Output voltage | VO | 0 | V | 4 | |||
| Input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 4 | ||
| Input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 4 | |
| Input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 4 | ||
| Supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| Input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 3 | |
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 3 | |
| Output current | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 3 | |
| Supply current | ICC | 50 | mA | 3 | |||
| Ground current | IGND | -50 | mA | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Total power dissipation | Ptot | 500 | mW | 3 | |||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC = 2.0 V; 25 °C | 4 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC = 4.5 V; 25 °C | 4 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC = 6.0 V; 25 °C | 4 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC = 2.0 V; 25 °C | 4 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC = 4.5 V; 25 °C | 4 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC = 6.0 V; 25 °C | 4 | |
| HIGH-level output voltage | VOH | 1.9 | 2 | V | VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; 25 °C | 4 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; 25 °C | 4 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; 25 °C | 4 | |
| HIGH-level output voltage | VOH | 3.98 | 4.32 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; 25 °C | 4 | |
| HIGH-level output voltage | VOH | 5.48 | 5.81 | V | VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; 25 °C | 4 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; 25 °C | 4 | |
| LOW-level output voltage | VOL | 0.15 | 0.26 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; 25 °C | 4 | |
| LOW-level output voltage | VOL | 0.16 | 0.26 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; 25 °C | 4 | |
| Input leakage current | II | -0.1 | 0.1 | μA | VI = VCC or GND; VCC = 6.0 V; 25 °C | 4 | |
| Input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 4 | |
| Supply current | ICC | 2 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; 25 °C | 4 | ||
| Supply current | ICC | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 4 | ||
| Propagation delay nA, nB to nY | tpd | 39 | 120 | ns | VCC = 2.0 V; 25 °C; see Fig. 4 | 5 | |
| Propagation delay nA, nB to nY | tpd | 14 | 24 | ns | VCC = 4.5 V; 25 °C; see Fig. 4 | 5 | |
| Propagation delay nA, nB to nY | tpd | 11 | 20 | ns | VCC = 6.0 V; 25 °C; see Fig. 4 | 5 | |
| Transition time nY | tt | 19 | 75 | ns | VCC = 2.0 V; 25 °C; see Fig. 4 | 5 | |
| Transition time nY | tt | 7 | 15 | ns | VCC = 4.5 V; 25 °C; see Fig. 4 | 5 | |
| Transition time nY | tt | 6 | 13 | ns | VCC = 6.0 V; 25 °C; see Fig. 4 | 5 | |
| Propagation delay nA, nB to nY | tpd | 180 | ns | VCC = 2.0 V; -40 °C to +125 °C; see Fig. 4 | 5 | ||
| Propagation delay nA, nB to nY | tpd | 36 | ns | VCC = 4.5 V; -40 °C to +125 °C; see Fig. 4 | 5 | ||
| Propagation delay nA, nB to nY | tpd | 31 | ns | VCC = 6.0 V; -40 °C to +125 °C; see Fig. 4 | 5 | ||
| Transition time nY | tt | 110 | ns | VCC = 2.0 V; -40 °C to +125 °C; see Fig. 4 | 5 | ||
| Transition time nY | tt | 22 | ns | VCC = 4.5 V; -40 °C to +125 °C; see Fig. 4 | 5 | ||
| Transition time nY | tt | 19 | ns | VCC = 6.0 V; -40 °C to +125 °C; see Fig. 4 | 5 | ||
| Propagation delay nA, nB to nY | tpd | 11 | ns | VCC = 5.0 V; CL = 15 pF; 25 °C | 5 | ||
| Power dissipation capacitance | CPD | 30 | pF | per package; VI = GND to VCC; 25 °C | 5 | ||
| Input capacitance | CI | 3.5 | pF | 4 |
CAD (KiCad official)
- Symbol:
74HC86PW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74hc86pw-etched.step/74hc86pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc86pw.step/74hc86pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (12 pp, sha256
efb3cf17b91fff76, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74HC86PW
**Nexperia** · Logic Gates · TSSOP-14
74HC86PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of the first EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 2 | 1B | input | Data input 1B of the first EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 3 | 1Y | output | Data output 1Y of the first EXCLUSIVE-OR gate, which goes HIGH only when inputs 1A and 1B differ. |
| 4 | 2A | input | Data input 2A of the second EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 5 | 2B | input | Data input 2B of the second EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 6 | 2Y | output | Data output 2Y of the second EXCLUSIVE-OR gate, which goes HIGH only when inputs 2A and 2B differ. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 3Y | output | Data output 3Y of the third EXCLUSIVE-OR gate, which goes HIGH only when inputs 3A and 3B differ. |
| 9 | 3A | input | Data input 3A of the third EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 10 | 3B | input | Data input 3B of the third EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 11 | 4Y | output | Data output 4Y of the fourth EXCLUSIVE-OR gate, which goes HIGH only when inputs 4A and 4B differ. |
| 12 | 4A | input | Data input 4A of the fourth EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 13 | 4B | input | Data input 4B of the fourth EXCLUSIVE-OR gate; inputs include clamp diodes, so current-limiting resistors can interface inputs to voltages above VCC. |
| 14 | VCC | power_in | Supply voltage; recommended range is 2.0 V to 6.0 V for 74HC86 and 4.5 V to 5.5 V for 74HCT86. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 2 | 5 | 6 | V | | 4 |
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | | 4 |
| Input voltage | VI | 0 | | | V | | 4 |
| Output voltage | VO | 0 | | | V | | 4 |
| Input transition rise and fall rate | Δt/ΔV | | | 625 | ns/V | VCC = 2.0 V | 4 |
| Input transition rise and fall rate | Δt/ΔV | | 1.67 | 139 | ns/V | VCC = 4.5 V | 4 |
| Input transition rise and fall rate | Δt/ΔV | | | 83 | ns/V | VCC = 6.0 V | 4 |
| Supply voltage | VCC | -0.5 | | 7 | V | | 3 |
| Input clamping current | IIK | -20 | | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 3 |
| Output clamping current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 3 |
| Output current | IO | -25 | | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 3 |
| Supply current | ICC | | | 50 | mA | | 3 |
| Ground current | IGND | -50 | | | mA | | 3 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 3 |
| Total power dissipation | Ptot | | | 500 | mW | | 3 |
| HIGH-level input voltage | VIH | 1.5 | 1.2 | | V | VCC = 2.0 V; 25 °C | 4 |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | | V | VCC = 4.5 V; 25 °C | 4 |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | | V | VCC = 6.0 V; 25 °C | 4 |
| LOW-level input voltage | VIL | | 0.8 | 0.5 | V | VCC = 2.0 V; 25 °C | 4 |
| LOW-level input voltage | VIL | | 2.1 | 1.35 | V | VCC = 4.5 V; 25 °C | 4 |
| LOW-level input voltage | VIL | | 2.8 | 1.8 | V | VCC = 6.0 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 1.9 | 2 | | V | VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | | V | VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 5.9 | 6 | | V | VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 3.98 | 4.32 | | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; 25 °C | 4 |
| HIGH-level output voltage | VOH | 5.48 | 5.81 | | V | VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; 25 °C | 4 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; 25 °C | 4 |
| LOW-level output voltage | VOL | | 0.15 | 0.26 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; 25 °C | 4 |
| LOW-level output voltage | VOL | | 0.16 | 0.26 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; 25 °C | 4 |
| Input leakage current | II | -0.1 | | 0.1 | μA | VI = VCC or GND; VCC = 6.0 V; 25 °C | 4 |
| Input leakage current | II | -1 | | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 4 |
| Supply current | ICC | | | 2 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; 25 °C | 4 |
| Supply current | ICC | | | 40 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 4 |
| Propagation delay nA, nB to nY | tpd | | 39 | 120 | ns | VCC = 2.0 V; 25 °C; see Fig. 4 | 5 |
| Propagation delay nA, nB to nY | tpd | | 14 | 24 | ns | VCC = 4.5 V; 25 °C; see Fig. 4 | 5 |
| Propagation delay nA, nB to nY | tpd | | 11 | 20 | ns | VCC = 6.0 V; 25 °C; see Fig. 4 | 5 |
| Transition time nY | tt | | 19 | 75 | ns | VCC = 2.0 V; 25 °C; see Fig. 4 | 5 |
| Transition time nY | tt | | 7 | 15 | ns | VCC = 4.5 V; 25 °C; see Fig. 4 | 5 |
| Transition time nY | tt | | 6 | 13 | ns | VCC = 6.0 V; 25 °C; see Fig. 4 | 5 |
| Propagation delay nA, nB to nY | tpd | | | 180 | ns | VCC = 2.0 V; -40 °C to +125 °C; see Fig. 4 | 5 |
| Propagation delay nA, nB to nY | tpd | | | 36 | ns | VCC = 4.5 V; -40 °C to +125 °C; see Fig. 4 | 5 |
| Propagation delay nA, nB to nY | tpd | | | 31 | ns | VCC = 6.0 V; -40 °C to +125 °C; see Fig. 4 | 5 |
| Transition time nY | tt | | | 110 | ns | VCC = 2.0 V; -40 °C to +125 °C; see Fig. 4 | 5 |
| Transition time nY | tt | | | 22 | ns | VCC = 4.5 V; -40 °C to +125 °C; see Fig. 4 | 5 |
| Transition time nY | tt | | | 19 | ns | VCC = 6.0 V; -40 °C to +125 °C; see Fig. 4 | 5 |
| Propagation delay nA, nB to nY | tpd | | 11 | | ns | VCC = 5.0 V; CL = 15 pF; 25 °C | 5 |
| Power dissipation capacitance | CPD | | 30 | | pF | per package; VI = GND to VCC; 25 °C | 5 |
| Input capacitance | CI | | 3.5 | | pF | | 4 |
## CAD (KiCad official)
- Symbol: `74HC86PW`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `74hc86pw-etched.step` / `74hc86pw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc86pw.step` / `74hc86pw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74HC86PW.pdf) (12 pp, sha256 `efb3cf17b91fff76`, retrieved 2026-10-17, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74hc86pw-datasheet.pdf)