component
74HC74PW-Q100
Public Made by Adomby adom
Nexperia Flip Flops, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC74PW-Q100
Nexperia · Flip Flops · TSSOP-14
74HC74PW-Q100 from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1RD | input | Asynchronous reset-direct input, active LOW; when LOW it forces 1Q LOW and 1Q HIGH independent of the clock. |
| 2 | 1D | input | Data input for flip-flop 1; the level must meet set-up and hold times around the LOW-to-HIGH transition of 1CP to be stored. |
| 3 | 1CP | input | Clock input for flip-flop 1, edge-triggered on the LOW-to-HIGH transition, with a Schmitt-trigger input that tolerates slow clock edges. |
| 4 | 1SD | input | Asynchronous set-direct input, active LOW; when LOW it forces 1Q HIGH and 1Q LOW independent of the clock. |
| 5 | 1Q | output | True output of flip-flop 1. |
| 6 | 1Q | output | Complement output of flip-flop 1, the inverse of 1Q. |
| 7 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 8 | 2Q | output | Complement output of flip-flop 2, the inverse of 2Q. |
| 9 | 2Q | output | True output of flip-flop 2. |
| 10 | 2SD | input | Asynchronous set-direct input, active LOW; when LOW it forces 2Q HIGH and 2Q LOW independent of the clock. |
| 11 | 2CP | input | Clock input for flip-flop 2, edge-triggered on the LOW-to-HIGH transition, with a Schmitt-trigger input that tolerates slow clock edges. |
| 12 | 2D | input | Data input for flip-flop 2; the level must meet set-up and hold times around the LOW-to-HIGH transition of 2CP to be stored. |
| 13 | 2RD | input | Asynchronous reset-direct input, active LOW; when LOW it forces 2Q LOW and 2Q HIGH independent of the clock. |
| 14 | VCC | power_in | Supply voltage; recommended 2.0 V to 6.0 V for 74HC74-Q100 and 4.5 V to 5.5 V for 74HCT74-Q100. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | 4 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| output current | IO | -25 | 25 | mA | VO = -0.5 V to (VCC + 0.5 V) | 4 | |
| supply current | ICC | 100 | mA | 4 | |||
| ground current | IGND | -100 | mA | 4 | |||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 4 | ||
| supply voltage (74HC74-Q100) | VCC | 2 | 5 | 6 | V | 5 | |
| input voltage (74HC74-Q100) | VI | 0 | V | 5 | |||
| output voltage (74HC74-Q100) | VO | 0 | V | 5 | |||
| ambient temperature | Tamb | -40 | 25 | 125 | °C | 5 | |
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 5 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 5 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 5 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | -40 °C to +85 °C; VCC = 2.0 V | 6 | |
| HIGH-level input voltage | VIH | 1.5 | V | -40 °C to +125 °C; VCC = 2.0 V | 6 | ||
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | -40 °C to +85 °C; VCC = 4.5 V | 6 | |
| HIGH-level input voltage | VIH | 3.15 | V | -40 °C to +125 °C; VCC = 4.5 V | 6 | ||
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | -40 °C to +85 °C; VCC = 6.0 V | 6 | |
| HIGH-level input voltage | VIH | 4.2 | V | -40 °C to +125 °C; VCC = 6.0 V | 6 | ||
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | -40 °C to +85 °C; VCC = 2.0 V | 6 | |
| LOW-level input voltage | VIL | 0.5 | V | -40 °C to +125 °C; VCC = 2.0 V | 6 | ||
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | -40 °C to +85 °C; VCC = 4.5 V | 6 | |
| LOW-level input voltage | VIL | 1.35 | V | -40 °C to +125 °C; VCC = 4.5 V | 6 | ||
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | -40 °C to +85 °C; VCC = 6.0 V | 6 | |
| LOW-level input voltage | VIL | 1.8 | V | -40 °C to +125 °C; VCC = 6.0 V | 6 | ||
| HIGH-level output voltage | VOH | 3.84 | 4.32 | V | -40 °C to +85 °C; VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V | 6 | |
| HIGH-level output voltage | VOH | 3.7 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V | 6 | ||
| HIGH-level output voltage | VOH | 5.34 | 5.81 | V | -40 °C to +85 °C; VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V | 6 | |
| HIGH-level output voltage | VOH | 5.2 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V | 6 | ||
| LOW-level output voltage | VOL | 0.15 | 0.33 | V | -40 °C to +85 °C; VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V | 6 | |
| LOW-level output voltage | VOL | 0.4 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V | 6 | ||
| LOW-level output voltage | VOL | 0.16 | 0.33 | V | -40 °C to +85 °C; VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V | 6 | |
| input leakage current | II | -1 | 1 | μA | -40 °C to +85 °C; VI = VCC or GND; VCC = 6.0 V | 6 | |
| supply current | ICC | 40 | μA | -40 °C to +85 °C; VI = VCC or GND; IO = 0 A; VCC = 6.0 V | 6 | ||
| supply current | ICC | 80 | μA | -40 °C to +125 °C; VI = VCC or GND; IO = 0 A; VCC = 6.0 V | 6 | ||
| propagation delay | tpd | 17 | 44 | ns | -40 °C to +85 °C; nCP to nQ, nQ; see Fig. 5; VCC = 4.5 V | 7 | |
| propagation delay | tpd | 53 | ns | -40 °C to +125 °C; nCP to nQ, nQ; see Fig. 5; VCC = 4.5 V | 7 | ||
| propagation delay | tpd | 18 | 50 | ns | -40 °C to +85 °C; nSD to nQ, nQ; see Fig. 6; VCC = 4.5 V | 7 | |
| propagation delay | tpd | 60 | ns | -40 °C to +125 °C; nSD to nQ, nQ; see Fig. 6; VCC = 4.5 V | 7 | ||
| propagation delay | tpd | 19 | 50 | ns | -40 °C to +85 °C; nRD to nQ, nQ; see Fig. 6; VCC = 4.5 V | 7 | |
| transition time | tt | 7 | 19 | ns | -40 °C to +85 °C; nQ, nQ; see Fig. 5; VCC = 4.5 V | 7 | |
| transition time | tt | 22 | ns | -40 °C to +125 °C; nQ, nQ; see Fig. 5; VCC = 4.5 V | 7 | ||
| pulse width | tW | 20 | 7 | ns | -40 °C to +85 °C; nCP HIGH or LOW; see Fig. 5; VCC = 4.5 V | 7 | |
| pulse width | tW | 24 | ns | -40 °C to +125 °C; nCP HIGH or LOW; see Fig. 5; VCC = 4.5 V | 7 | ||
| recovery time | trec | 8 | 1 | ns | -40 °C to +85 °C; nSD, nRD; see Fig. 6; VCC = 4.5 V | 7 | |
| recovery time | trec | 9 | ns | -40 °C to +125 °C; nSD, nRD; see Fig. 6; VCC = 4.5 V | 7 | ||
| set-up time | tsu | 15 | 2 | ns | -40 °C to +85 °C; nD to nCP; see Fig. 5; VCC = 4.5 V | 8 | |
| set-up time | tsu | 18 | ns | -40 °C to +125 °C; nD to nCP; see Fig. 5; VCC = 4.5 V | 8 | ||
| hold time | th | 3 | -2 | ns | -40 °C to +85 °C; nD to nCP; see Fig. 5; VCC = 4.5 V | 8 | |
| hold time | th | 3 | ns | -40 °C to +125 °C; nD to nCP; see Fig. 5; VCC = 4.5 V | 8 | ||
| maximum frequency | fmax | 24 | 69 | MHz | -40 °C to +85 °C; nCP; see Fig. 5; VCC = 4.5 V | 8 | |
| maximum frequency | fmax | 20 | MHz | -40 °C to +125 °C; nCP; see Fig. 5; VCC = 4.5 V | 8 |
CAD (KiCad official)
- Symbol:
74HC74PW-Q100 - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
74hc74pw-q100-etched.step/74hc74pw-q100-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc74pw-q100.step/74hc74pw-q100.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (18 pp, sha256
5b865b51d6a373a9, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).