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74HC74D-Q100

Public Made by Adom

by adom

Nexperia Flip Flops, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC74D-Q100

Nexperia · Flip Flops · SOP-14

74HC74D-Q100 from Nexperia, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1RD input Asynchronous reset-direct input for flip-flop 1, active LOW; with 1SD HIGH, a LOW on 1RD forces 1Q LOW and 1Q HIGH.
2 1D input Data input for flip-flop 1; data that meets set-up and hold time at the LOW-to-HIGH clock transition is stored and appears at 1Q.
3 1CP input Clock input for flip-flop 1, positive edge-triggered (LOW-to-HIGH); the Schmitt-trigger input tolerates slow clock rise and fall times.
4 1SD input Asynchronous set-direct input for flip-flop 1, active LOW; with 1RD HIGH, a LOW on 1SD forces 1Q HIGH and 1Q LOW.
5 1Q output True output of flip-flop 1.
6 1Q output Complement output of flip-flop 1 (the inverse of 1Q).
7 GND power_in Ground (0 V) reference for all voltages.
8 2Q output Complement output of flip-flop 2 (the inverse of 2Q).
9 2Q output True output of flip-flop 2.
10 2SD input Asynchronous set-direct input for flip-flop 2, active LOW.
11 2CP input Clock input for flip-flop 2, positive edge-triggered (LOW-to-HIGH); the Schmitt-trigger input tolerates slow clock rise and fall times.
12 2D input Data input for flip-flop 2; data that meets set-up and hold time at the LOW-to-HIGH clock transition is stored and appears at 2Q.
13 2RD input Asynchronous reset-direct input for flip-flop 2, active LOW.
14 VCC power_in Supply voltage; 2.0 V to 6.0 V for the 74HC74-Q100 and 4.5 V to 5.5 V for the 74HCT74-Q100 per the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2 5 6 V 5
Input voltage VI 0 V 5
Output voltage VO 0 V 5
Ambient temperature Tamb -40 25 125 °C 5
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 5
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 5
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 5
Supply voltage VCC -0.5 7 V 4
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
Output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 4
Supply current ICC 100 mA 4
Ground current IGND -100 mA 4
Storage temperature Tstg -65 150 °C 4
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V; -40 °C to +125 °C 6
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V; -40 °C to +125 °C 6
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V; -40 °C to +125 °C 6
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V; -40 °C to +125 °C 6
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V; -40 °C to +125 °C 6
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V; -40 °C to +125 °C 6
HIGH-level output voltage VOH 3.7 4.32 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +125 °C 6
HIGH-level output voltage VOH 5.2 5.81 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; -40 °C to +125 °C 6
LOW-level output voltage VOL 0.15 0.4 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C 6
LOW-level output voltage VOL 0.16 0.4 V VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; -40 °C to +125 °C 6
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C 6
Supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C 6
Propagation delay nCP to nQ, nQ tpd 47 265 ns VCC = 2.0 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C 7
Propagation delay nCP to nQ, nQ tpd 17 53 ns VCC = 4.5 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C 7
Propagation delay nCP to nQ, nQ tpd 14 45 ns VCC = 6.0 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C 7
Propagation delay nSD to nQ, nQ tpd 50 300 ns VCC = 2.0 V; CL = 50 pF; see Fig. 6; -40 °C to +125 °C 7
Propagation delay nSD to nQ, nQ tpd 18 60 ns VCC = 4.5 V; CL = 50 pF; see Fig. 6; -40 °C to +125 °C 7
Propagation delay nSD to nQ, nQ tpd 14 51 ns VCC = 6.0 V; CL = 50 pF; see Fig. 6; -40 °C to +125 °C 7
Propagation delay nRD to nQ, nQ tpd 52 300 ns VCC = 2.0 V; CL = 50 pF; see Fig. 6; -40 °C to +125 °C 7
Propagation delay nRD to nQ, nQ tpd 19 60 ns VCC = 4.5 V; CL = 50 pF; see Fig. 6; -40 °C to +125 °C 7
Propagation delay nRD to nQ, nQ tpd 15 51 ns VCC = 6.0 V; CL = 50 pF; see Fig. 6; -40 °C to +125 °C 7
Transition time nQ, nQ tt 19 110 ns VCC = 2.0 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C 7
Transition time nQ, nQ tt 7 22 ns VCC = 4.5 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C 7
Transition time nQ, nQ tt 6 19 ns VCC = 6.0 V; CL = 50 pF; see Fig. 5; -40 °C to +125 °C 7
Pulse width nCP HIGH or LOW tW 120 19 ns VCC = 2.0 V; see Fig. 5; -40 °C to +125 °C 7
Pulse width nCP HIGH or LOW tW 24 7 ns VCC = 4.5 V; see Fig. 5; -40 °C to +125 °C 7
Pulse width nCP HIGH or LOW tW 20 6 ns VCC = 6.0 V; see Fig. 5; -40 °C to +125 °C 7
Pulse width nSD, nRD LOW tW 120 19 ns VCC = 2.0 V; see Fig. 6; -40 °C to +125 °C 7
Pulse width nSD, nRD LOW tW 24 7 ns VCC = 4.5 V; see Fig. 6; -40 °C to +125 °C 7
Pulse width nSD, nRD LOW tW 20 6 ns VCC = 6.0 V; see Fig. 6; -40 °C to +125 °C 7
Recovery time nSD, nRD trec 45 3 ns VCC = 2.0 V; see Fig. 6; -40 °C to +125 °C 7
Recovery time nSD, nRD trec 9 1 ns VCC = 4.5 V; see Fig. 6; -40 °C to +125 °C 7
Recovery time nSD, nRD trec 8 1 ns VCC = 6.0 V; see Fig. 6; -40 °C to +125 °C 7
Set-up time nD to nCP tsu 90 6 ns VCC = 2.0 V; see Fig. 5; -40 °C to +125 °C 8
Set-up time nD to nCP tsu 18 2 ns VCC = 4.5 V; see Fig. 5; -40 °C to +125 °C 8
Set-up time nD to nCP tsu 15 2 ns VCC = 6.0 V; see Fig. 5; -40 °C to +125 °C 8
Hold time nD to nCP th 3 -6 ns VCC = 2.0 V; see Fig. 5; -40 °C to +125 °C 8
Hold time nD to nCP th 3 -2 ns VCC = 4.5 V; see Fig. 5; -40 °C to +125 °C 8
Maximum frequency nCP fmax 4 23 MHz VCC = 2.0 V; see Fig. 5; -40 °C to +125 °C 8
Maximum frequency nCP fmax 20 69 MHz VCC = 4.5 V; see Fig. 5; -40 °C to +125 °C 8
Maximum frequency nCP fmax 24 82 MHz VCC = 6.0 V; see Fig. 5; -40 °C to +125 °C 8

CAD (KiCad official)

  • Symbol: 74HC74D-Q100
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74hc74d-q100-etched.step / 74hc74d-q100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc74d-q100.step / 74hc74d-q100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (18 pp, sha256 5b865b51d6a373a9, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF