component

74HC73PW

Public Made by Adom

by adom

Nexperia Flip Flops, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogic74hc73pwfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers 74hc73pw: viewers · Ray 5d ago
74hc73pw-etched.glb Publish 0.1.0 · Ray 5d ago
74hc73pw-etched.step 74hc73pw: factory component page (tier=mfr) · Ray 5d ago
74hc73pw-hero.glb 74hc73pw: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
74hc73pw-hero.overlay.json Publish 0.1.0 · Ray 5d ago
74hc73pw.glb Publish 0.1.0 · Ray 5d ago
74hc73pw.kicad_mod Publish 0.1.0 · Ray 5d ago
74hc73pw.kicad_sym Publish 0.1.0 · Ray 5d ago
74hc73pw.lbr Publish 0.1.0 · Ray 5d ago
74hc73pw.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago

74HC73PW

Nexperia · Flip Flops · TSSOP-14

74HC73PW from Nexperia, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CP input Clock input for flip-flop 1, HIGH-to-LOW edge-triggered with Schmitt-trigger action, also referred to as nCP.
2 1R input Asynchronous reset input for flip-flop 1, active LOW, which overrides the clock and data inputs when LOW.
3 1K input Synchronous K input for flip-flop 1, which must be stable one set-up time before the HIGH-to-LOW clock transition, also referred to as nK.
4 VCC power_in Positive supply voltage, specified from 2.0 V to 6.0 V.
5 2CP input Clock input for flip-flop 2, HIGH-to-LOW edge-triggered with Schmitt-trigger action, also referred to as nCP.
6 2R input Asynchronous reset input for flip-flop 2, active LOW, which overrides the clock and data inputs when LOW.
7 2J input Synchronous J input for flip-flop 2, which must be stable one set-up time before the HIGH-to-LOW clock transition, also referred to as nJ.
8 ~{2Q} output Complement output of flip-flop 2, also referred to as nQ̄.
9 2Q output True output of flip-flop 2, also referred to as nQ.
10 2K input Synchronous K input for flip-flop 2, which must be stable one set-up time before the HIGH-to-LOW clock transition, also referred to as nK.
11 GND power_in Ground reference at 0 V.
12 1Q output True output of flip-flop 1, also referred to as nQ.
13 ~{1Q} output Complement output of flip-flop 1, also referred to as nQ̄.
14 1J input Synchronous J input for flip-flop 1, which must be stable one set-up time before the HIGH-to-LOW clock transition, also referred to as nJ.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 4
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
Output current IO -25 25 mA VO = -0.5 V to VCC + 0.5 V 4
Supply current ICC 50 mA 4
Ground current IGND -50 mA 4
Storage temperature Tstg -65 150 °C 4
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
Supply voltage VCC 2 5 6 V 4
Input voltage VI 0 V max VCC 4
Output voltage VO 0 V max VCC 4
Ambient temperature Tamb -40 125 °C 4
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 4
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 4
HIGH-level input voltage VIH 1.5 V VCC = 2.0 V 4
HIGH-level input voltage VIH 3.15 V VCC = 4.5 V 4
HIGH-level input voltage VIH 4.2 V VCC = 6.0 V 4
LOW-level input voltage VIL 0.5 V VCC = 2.0 V 4
LOW-level input voltage VIL 1.35 V VCC = 4.5 V 4
LOW-level input voltage VIL 1.8 V VCC = 6.0 V 4
HIGH-level output voltage VOH 1.9 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V 5
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V 5
HIGH-level output voltage VOH 5.9 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V 5
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO = -4 mA; VCC = 4.5 V 5
HIGH-level output voltage VOH 5.2 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V 5
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V 5
LOW-level output voltage VOL 0.4 V VI = VIH or VIL; IO = 4 mA; VCC = 4.5 V 5
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V 5
Supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V 5
Propagation delay nCP to nQ tpd 240 ns nCP to nQ; see Fig. 7; VCC = 2.0 V; CL = 50 pF 5
Propagation delay nCP to nQ tpd 48 ns nCP to nQ; see Fig. 7; VCC = 4.5 V; CL = 50 pF 5
Propagation delay nCP to nQ tpd 41 ns nCP to nQ; see Fig. 7; VCC = 6.0 V; CL = 50 pF 5
Propagation delay nR to nQ, nQ tpd 220 ns nR to nQ, nQ; see Fig. 8; VCC = 2.0 V; CL = 50 pF 5
Propagation delay nR to nQ, nQ tpd 44 ns nR to nQ, nQ; see Fig. 8; VCC = 4.5 V; CL = 50 pF 5
Propagation delay nR to nQ, nQ tpd 38 ns nR to nQ, nQ; see Fig. 8; VCC = 6.0 V; CL = 50 pF 5
Transition time tt 110 ns nQ, nQ; see Fig. 7; VCC = 2.0 V 6
Transition time tt 22 ns nQ, nQ; see Fig. 7; VCC = 4.5 V 6
Transition time tt 19 ns nQ, nQ; see Fig. 7; VCC = 6.0 V 6
Pulse width tW 120 ns nCP input, HIGH or LOW; see Fig. 7; VCC = 2.0 V 6
Pulse width tW 24 ns nCP input, HIGH or LOW; see Fig. 7; VCC = 4.5 V 6
Pulse width tW 20 ns nCP input, HIGH or LOW; see Fig. 7; VCC = 6.0 V 6
Recovery time trec 120 ns nR to nCP; see Fig. 8; VCC = 2.0 V 6
Recovery time trec 24 ns nR to nCP; see Fig. 8; VCC = 4.5 V 6
Recovery time trec 20 ns nR to nCP; see Fig. 8; VCC = 6.0 V 6
Set-up time tsu 120 ns nJ, nK to nCP; see Fig. 7; VCC = 2.0 V 6
Set-up time tsu 24 ns nJ, nK to nCP; see Fig. 7; VCC = 4.5 V 6
Set-up time tsu 20 ns nJ, nK to nCP; see Fig. 7; VCC = 6.0 V 6
Hold time th 3 ns nJ, nK to nCP; see Fig. 7; VCC = 2.0 V 6
Maximum frequency fmax 4 MHz nCP input; see Fig. 7; VCC = 2.0 V 6
Maximum frequency fmax 20 MHz nCP input; see Fig. 7; VCC = 4.5 V 6
Maximum frequency fmax 24 MHz nCP input; see Fig. 7; VCC = 6.0 V 6

CAD (KiCad official)

  • Symbol: 74HC73PW
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: 74hc73pw-etched.step / 74hc73pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc73pw.step / 74hc73pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (13 pp, sha256 fa0accacf327f8fa, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF