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74HC597PW-Q100J

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Nexperia Logic ICs, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC597PW-Q100J

Nexperia · Logic ICs · TSSOP-16

74HC597PW-Q100J from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D1 input Parallel data input D1 to the 8-bit storage register, with clamp diodes that allow current-limited interfacing to voltages above VCC.
2 D2 input Parallel data input D2 to the 8-bit storage register, with clamp diodes that allow current-limited interfacing to voltages above VCC.
3 D3 input Parallel data input D3 to the 8-bit storage register, with clamp diodes that allow current-limited interfacing to voltages above VCC.
4 D4 input Parallel data input D4 to the 8-bit storage register, with clamp diodes that allow current-limited interfacing to voltages above VCC.
5 D5 input Parallel data input D5 to the 8-bit storage register, with clamp diodes that allow current-limited interfacing to voltages above VCC.
6 D6 input Parallel data input D6 to the 8-bit storage register, with clamp diodes that allow current-limited interfacing to voltages above VCC.
7 D7 input Parallel data input D7 to the 8-bit storage register, with clamp diodes that allow current-limited interfacing to voltages above VCC.
8 GND power_in Ground (0 V) reference for all voltages on the device.
9 Q output Serial data output of the 8-bit shift register.
10 MR input Asynchronous master reset input, active LOW, which clears the shift register.
11 SHCP input Shift register clock input, triggered on the LOW-to-HIGH edge.
12 STCP input Storage register clock input, triggered on the LOW-to-HIGH edge.
13 PL input Parallel load input, active LOW, which transfers data from the storage register into the shift register.
14 DS input Serial data input to the shift register.
15 D0 input Parallel data input D0 to the 8-bit storage register, with clamp diodes that allow current-limited interfacing to voltages above VCC.
16 VCC power_in Supply voltage; the datasheet gives a recommended range of 2.0 V to 6.0 V for 74HC597-Q100 and 4.5 V to 5.5 V for 74HCT597-Q100.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 5
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 5
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 5
Output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 5
Supply current ICC 50 mA 5
Ground current IGND -50 mA 5
Storage temperature Tstg -65 150 °C 5
Total power dissipation Ptot 500 mW SOT403-1 (TSSOP16): derates linearly with 8.5 mW/K above 91 °C 5
Supply voltage VCC 2 5 6 V 74HC597-Q100 6
Input voltage VI 0 V 6
Output voltage VO 0 V 6
Ambient temperature Tamb -40 25 125 °C 6
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 6
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 6
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 6
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V; 25 °C 6
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V; 25 °C 6
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V; 25 °C 6
HIGH-level input voltage VIH 1.5 V VCC = 2.0 V; -40 °C to +85 °C 6
HIGH-level input voltage VIH 3.15 V VCC = 4.5 V; -40 °C to +85 °C 6
HIGH-level input voltage VIH 4.2 V VCC = 6.0 V; -40 °C to +85 °C 6
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V; 25 °C 6
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V; 25 °C 6
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V; 25 °C 6
LOW-level input voltage VIL 0.5 V VCC = 2.0 V; -40 °C to +85 °C 6
LOW-level input voltage VIL 1.35 V VCC = 4.5 V; -40 °C to +85 °C 6
LOW-level input voltage VIL 1.8 V VCC = 6.0 V; -40 °C to +85 °C 6
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; 25 °C 6
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; 25 °C 6
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; 25 °C 6
HIGH-level output voltage VOH 3.98 4.32 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; 25 °C 6
HIGH-level output voltage VOH 5.48 5.81 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; 25 °C 6
HIGH-level output voltage VOH 1.9 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; -40 °C to +125 °C 6
HIGH-level output voltage VOH 4.4 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +125 °C 6
HIGH-level output voltage VOH 5.9 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; -40 °C to +125 °C 6
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +125 °C 6
HIGH-level output voltage VOH 5.2 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; -40 °C to +125 °C 6
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; 25 °C 6
LOW-level output voltage VOL 0.15 0.26 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; 25 °C 6
LOW-level output voltage VOL 0.16 0.26 V VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; 25 °C 6
LOW-level output voltage VOL 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C 6
LOW-level output voltage VOL 0.4 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C 6
Input leakage current II -0.1 0.1 μA VI = VCC or GND; VCC = 6.0 V; 25 °C 6
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C 6
Supply current ICC 8 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; 25 °C 6
Supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C 6

CAD (KiCad official)

  • Symbol: 74HC597PW-Q100J
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc597pw-q100j-etched.step / 74hc597pw-q100j-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc597pw-q100j.step / 74hc597pw-q100j.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (18 pp, sha256 11e4fcaace0cc10e, retrieved 2026-10-17, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF