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74HC597D

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Nexperia Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC597D

Nexperia · Shift Registers · SOIC-16

74HC597D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D1 input Parallel data input D1 is loaded into the input flip-flops on the LOW-to-HIGH STCP clock edge.
2 D2 input Parallel data input D2 is loaded into the input flip-flops on the LOW-to-HIGH STCP clock edge.
3 D3 input Parallel data input D3 is loaded into the input flip-flops on the LOW-to-HIGH STCP clock edge.
4 D4 input Parallel data input D4 is loaded into the input flip-flops on the LOW-to-HIGH STCP clock edge.
5 D5 input Parallel data input D5 is loaded into the input flip-flops on the LOW-to-HIGH STCP clock edge.
6 D6 input Parallel data input D6 is loaded into the input flip-flops on the LOW-to-HIGH STCP clock edge.
7 D7 input Parallel data input D7 is loaded into the input flip-flops on the LOW-to-HIGH STCP clock edge.
8 GND power_in Ground (0 V) reference for all voltages.
9 Q output Serial data output of the 8-bit shift register.
10 MR input Asynchronous master reset input, active LOW, clears the shift register.
11 SHCP input Shift register clock input, triggered on the LOW-to-HIGH edge.
12 STCP input Storage register clock input, triggered on the LOW-to-HIGH edge.
13 PL input Parallel load input, active LOW, loads the storage register contents into the shift register.
14 DS input Serial data input to the shift register, shifted in on SHCP.
15 D0 input Parallel data input D0 is loaded into the input flip-flops on the LOW-to-HIGH STCP clock edge.
16 VCC power_in Supply voltage; the recommended range is 2.0 V to 6.0 V for 74HC597 and 4.5 V to 5.5 V for 74HCT597.

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 5
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 5
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 5
Output current IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V) 5
Supply current ICC 50 mA 5
Ground current IGND -50 mA 5
Storage temperature Tstg -65 150 °C 5
Total power dissipation Ptot 500 mW SOT109-1 (SO16); derates 12.4 mW/K above 110 °C 5
Supply voltage VCC 2 5 6 V 74HC597 6
Ambient temperature Tamb -40 25 125 °C 6
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 6
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 6
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 6
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V 6
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V 6
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V 6
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V 6
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V 6
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V 6
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V 6
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V 6
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V 6
HIGH-level output voltage VOH 3.7 4.32 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V 6
HIGH-level output voltage VOH 5.2 5.81 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V 6
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V 6
LOW-level output voltage VOL 0.15 0.4 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V 6
LOW-level output voltage VOL 0.16 0.4 V VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V 6
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V 6
Supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V 6
Propagation delay SHCP to Q tpd 55 265 ns VCC = 2.0 V; see Fig. 6 8
Propagation delay SHCP to Q tpd 20 53 ns VCC = 4.5 V; see Fig. 6 8
Propagation delay SHCP to Q tpd 16 45 ns VCC = 6.0 V; see Fig. 6 8
Propagation delay MR to Q tpd 58 265 ns VCC = 2.0 V; see Fig. 7 8
Propagation delay MR to Q tpd 21 53 ns VCC = 4.5 V; see Fig. 7 8
Propagation delay MR to Q tpd 17 45 ns VCC = 6.0 V; see Fig. 7 8
Propagation delay STCP to Q tpd 80 375 ns VCC = 2.0 V; see Fig. 6 8
Propagation delay STCP to Q tpd 29 75 ns VCC = 4.5 V; see Fig. 6 8
Propagation delay STCP to Q tpd 23 64 ns VCC = 6.0 V; see Fig. 6 8
Propagation delay PL to Q tpd 69 325 ns VCC = 2.0 V; see Fig. 8 8
Propagation delay PL to Q tpd 25 65 ns VCC = 4.5 V; see Fig. 8 8
Propagation delay PL to Q tpd 20 55 ns VCC = 6.0 V; see Fig. 8 8
STCP pulse width HIGH or LOW tW 120 11 ns VCC = 2.0 V; see Fig. 6 9
STCP pulse width HIGH or LOW tW 24 4 ns VCC = 4.5 V; see Fig. 6 9
STCP pulse width HIGH or LOW tW 20 3 ns VCC = 6.0 V; see Fig. 6 9
SHCP pulse width HIGH or LOW tW 120 14 ns VCC = 2.0 V; see Fig. 6 9
SHCP pulse width HIGH or LOW tW 24 5 ns VCC = 4.5 V; see Fig. 6 9
SHCP pulse width HIGH or LOW tW 20 4 ns VCC = 6.0 V; see Fig. 6 9
MR pulse width LOW tW 120 22 ns VCC = 2.0 V; see Fig. 7 9
MR pulse width LOW tW 24 8 ns VCC = 4.5 V; see Fig. 7 9
MR pulse width LOW tW 20 6 ns VCC = 6.0 V; see Fig. 7 9
PL pulse width LOW tW 120 22 ns VCC = 2.0 V; see Fig. 8 9
PL pulse width LOW tW 24 8 ns VCC = 4.5 V; see Fig. 8 9
PL pulse width LOW tW 20 6 ns VCC = 6.0 V; see Fig. 8 9
Maximum clock frequency SHCP fmax 4 29 MHz VCC = 2.0 V; see Fig. 6 10
Maximum clock frequency SHCP fmax 20 87 MHz VCC = 4.5 V; see Fig. 6 10
Maximum clock frequency SHCP fmax 24 104 MHz VCC = 6.0 V; see Fig. 6 10

CAD (KiCad official)

  • Symbol: 74HC597D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc597d-etched.step / 74hc597d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc597d.step / 74hc597d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (18 pp, sha256 5bc6b36a163e4fbd, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF