component
74HC595PW
Public Made by Adomby adom
Nexperia Shifting Register, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
74hc595pw: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body w…
8e440b6
15d ago
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"title": "74HC595PW",
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"version": "0.2.0",
"license": "CC-BY-SA-4.0",
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"manufacturer": "Nexperia",
"package": "TSSOP-16",
"pin_count": 16,
"category": "Logic",
"subcategory": "Shifting Register",
"datasheet": "https://assets.nexperia.com/documents/data-sheet/74HC595PW.pdf",
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"pins": [
{
"number": "1",
"name": "Q1",
"type": "output",
"description": "Parallel data output bit 1 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH. Bus driver output: sourcing/sinking up to ~6 mA at VCC = 4.5 V."
},
{
"number": "2",
"name": "Q2",
"type": "output",
"description": "Parallel data output bit 2 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH."
},
{
"number": "3",
"name": "Q3",
"type": "output",
"description": "Parallel data output bit 3 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH."
},
{
"number": "4",
"name": "Q4",
"type": "output",
"description": "Parallel data output bit 4 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH."
},
{
"number": "5",
"name": "Q5",
"type": "output",
"description": "Parallel data output bit 5 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH."
},
{
"number": "6",
"name": "Q6",
"type": "output",
"description": "Parallel data output bit 6 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH."
},
{
"number": "7",
"name": "Q7",
"type": "output",
"description": "Parallel data output bit 7 (MSB) from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH."
},
{
"number": "8",
"name": "GND",
"type": "power_in",
"description": "Ground reference (0 V). Connect to system ground."
},
{
"number": "9",
"name": "Q7S",
"type": "output",
"description": "Serial data output from the last stage of the shift register. Used to cascade multiple 74HC595 devices by tying to the next stage's DS input. Non-3-state; drives up to ~4 mA at VCC = 4.5 V."
},
{
"number": "10",
"name": "MR",
"type": "input",
"description": "Master reset input, active LOW. A LOW level asynchronously clears the shift register (does not affect the storage register/parallel outputs). Must be held HIGH during normal shift operation."
},
{
"number": "11",
"name": "SHCP",
"type": "input",
"description": "Shift register clock input. Data on DS is shifted into the shift register on the LOW-to-HIGH transition of SHCP. Equivalent to the SPI SCK for the shift stage; typical max frequency ~100 MHz at VCC = 6 V."
},
{
"number": "12",
"name": "STCP",
"type": "input",
"description": "Storage register clock input (latch). On the LOW-to-HIGH transition of STCP, the contents of the shift register are transferred to the storage register and appear on Q0..Q7. Commonly called the 'latch' or 'RCK' pin."
},
{
"number": "13",
"name": "OE",
"type": "input",
"description": "Output enable input, active LOW. LOW enables the Q0..Q7 parallel outputs; HIGH forces Q0..Q7 to a high-impedance OFF-state. Does not affect the state of the shift or storage registers."
},
{
"number": "14",
"name": "DS",
"type": "input",
"description": "Serial data input. Sampled into shift register stage 0 on the LOW-to-HIGH edge of SHCP. Equivalent to SPI MOSI for cascaded shift-register chains."
},
{
"number": "15",
"name": "Q0",
"type": "output",
"description": "Parallel data output bit 0 (LSB) from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH."
},
{
"number": "16",
"name": "VCC",
"type": "power_in",
"description": "Positive supply voltage. Operating range 2.0 V to 6.0 V (74HC595) / 4.5 V to 5.5 V (74HCT595). Absolute maximum 7 V. Decouple locally with a 100 nF ceramic capacitor to GND."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://assets.nexperia.com/documents/data-sheet/74HC595PW.pdf",
"pages": 21,
"sha256": "fa24207e780cd8c4",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
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"pin1": {
"pad": "1",
"at": [
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"corner": "top-left",
"source": "silk-marker",
"derived_from": "TSSOP-16_4.4x5mm_P0.65mm@sha256:fbac79fc5f310754",
"mark": "drawn"
},
"logic": {
"family_id": "74HC595",
"logic_family": "74HC",
"function_code": "595",
"function_class": "ShiftRegister",
"function_name": "8-Bit SIPO Shift Register with Output Latch",
"manufacturer": null,
"is_specialty": false
},
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"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
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"zmin_mm": -0.0,
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"footprint_binding": "identity",
"sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
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"seat": "z = 0",
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"sha256": "2baa4a045cfdf11821121d66c7e25db33a955ae7064e6d775e02e8f747fd6b1f",
"checked": "2026-10-19",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Nexperia",
"Package": "TSSOP-16",
"Category": "Logic",
"Pins": "16"
}
},
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
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"discovery_pitch": "74HC595PW (Nexperia) component page with datasheet-verified CAD.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
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"docs/74hc595pw-datasheet.pdf",
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"visibility": {
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},
"updated_at": "2026-09-24T15:03:12.620Z"
}