74HC595M

{
  "schema_version": 1,
  "type": "component",
  "slug": "74hc595m",
  "title": "74HC595M",
  "brief": "HGSEMI Shifting Register, SOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.2",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "74hc595m"
  ],
  "component": {
    "mpn": "74HC595M",
    "manufacturer": "HGSEMI",
    "package": "SOP-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shifting Register",
    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/a3fbc4f7888fd390190e6295c01a3aa8.pdf",
    "parts": {
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      "footprint": "74hc595m.kicad_mod",
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      "model_3d_plain": "74hc595m.glb",
      "model_3d_step": "74hc595m-etched.step",
      "model_3d_step_plain": "74hc595m.step",
      "lbr": "74hc595m.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "QB",
        "type": "tri_state",
        "description": "Parallel data output bit B. Tri-state; enabled when /G is low, high-Z when /G is high. Reflects the stored value in the output storage register."
      },
      {
        "number": "2",
        "name": "QC",
        "type": "tri_state",
        "description": "Parallel data output bit C. Tri-state; enabled when /G is low, high-Z when /G is high."
      },
      {
        "number": "3",
        "name": "QD",
        "type": "tri_state",
        "description": "Parallel data output bit D. Tri-state; enabled when /G is low, high-Z when /G is high."
      },
      {
        "number": "4",
        "name": "QE",
        "type": "tri_state",
        "description": "Parallel data output bit E. Tri-state; enabled when /G is low, high-Z when /G is high."
      },
      {
        "number": "5",
        "name": "QF",
        "type": "tri_state",
        "description": "Parallel data output bit F. Tri-state; enabled when /G is low, high-Z when /G is high."
      },
      {
        "number": "6",
        "name": "QG",
        "type": "tri_state",
        "description": "Parallel data output bit G. Tri-state; enabled when /G is low, high-Z when /G is high."
      },
      {
        "number": "7",
        "name": "QH",
        "type": "tri_state",
        "description": "Parallel data output bit H (MSB of the 8-bit storage register). Tri-state; enabled when /G is low, high-Z when /G is high."
      },
      {
        "number": "8",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference (0 V). Return for VCC."
      },
      {
        "number": "9",
        "name": "Q'H",
        "type": "output",
        "description": "Serial data output from the last stage (QH) of the shift register. Used to cascade multiple 74HC595 devices to form an 8n-bit shift register. Not tri-stated by /G."
      },
      {
        "number": "10",
        "name": "/SCLR",
        "type": "input",
        "description": "Active-low shift register clear. When held low, the 8-bit shift register is asynchronously reset to zero. Must be held high for normal shift operation."
      },
      {
        "number": "11",
        "name": "SCK",
        "type": "input",
        "description": "Shift register clock. Serial data on SER is sampled and shifted through the 8-bit register on the rising edge of SCK. Maximum frequency 10 MHz (typ, VCC=5V)."
      },
      {
        "number": "12",
        "name": "RCK",
        "type": "input",
        "description": "Storage (latch) register clock. On the rising edge of RCK, the current contents of the shift register are transferred to the 8-bit output storage register and appear at QA..QH."
      },
      {
        "number": "13",
        "name": "/G",
        "type": "input",
        "description": "Active-low output enable for the parallel outputs QA..QH. When low, outputs are driven; when high, QA..QH are placed in high-impedance (tri-state). Does not affect Q'H or the internal registers."
      },
      {
        "number": "14",
        "name": "SER",
        "type": "input",
        "description": "Serial data input. The logic level on SER is loaded into the first stage of the shift register on the rising edge of SCK."
      },
      {
        "number": "15",
        "name": "QA",
        "type": "tri_state",
        "description": "Parallel data output bit A (LSB of the 8-bit storage register). Tri-state; enabled when /G is low, high-Z when /G is high."
      },
      {
        "number": "16",
        "name": "VCC",
        "type": "power_in",
        "description": "Positive supply voltage. Operating range 3.2 V to 6 V (typ 5 V); absolute max 6.5 V. Bypass with a local 0.1 µF ceramic capacitor to GND."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://datasheet.lcsc.com/datasheet/pdf/a3fbc4f7888fd390190e6295c01a3aa8.pdf",
        "pages": 13,
        "sha256": "2466d95b2f765594",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -4.445
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "74HC595",
      "logic_family": "74HC",
      "function_code": "595",
      "function_class": "ShiftRegister",
      "function_name": "8-Bit SIPO Shift Register with Output Latch",
      "manufacturer": null,
      "is_specialty": false
    },
    "models_3d": [
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        "file": "74hc595m.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "74hc595m-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          9.9,
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "812a67fd5f40aee4fcfdfec75e852967ff71da3b1490835aa3099010f06f231b",
        "checked": "2026-11-12",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "HGSEMI",
      "Package": "SOP-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "sections": [
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    "breadcrumbs",
    "info"
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  "discovery_triggers": [
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  "discovery_pitch": "74HC595M (HGSEMI) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
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    "README.md",
    "74hc595m.kicad_sym",
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    "74hc595m-etched.step",
    "74hc595m.lbr",
    "docs/hero.png",
    "docs/74hc595m-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "pads.json",
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  "visibility": "public",
  "updated_at": "2026-09-24T15:02:53.358Z",
  "description": "HGSEMI Shifting Register, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",
  "org": "adom"
}