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74HC595DM

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HGSEMI Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC595DM

HGSEMI · Shift Registers · SOP-16

74HC595DM from HGSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 tri_state Parallel data output Q1 from the storage register; goes to high-impedance OFF-state when OE is HIGH.
2 Q2 tri_state Parallel data output Q2 from the storage register; goes to high-impedance OFF-state when OE is HIGH.
3 Q3 tri_state Parallel data output Q3 from the storage register; goes to high-impedance OFF-state when OE is HIGH.
4 Q4 tri_state Parallel data output Q4 from the storage register; goes to high-impedance OFF-state when OE is HIGH.
5 Q5 tri_state Parallel data output Q5 from the storage register; goes to high-impedance OFF-state when OE is HIGH.
6 Q6 tri_state Parallel data output Q6 from the storage register; goes to high-impedance OFF-state when OE is HIGH.
7 Q7 tri_state Parallel data output Q7 from the storage register; goes to high-impedance OFF-state when OE is HIGH.
8 GND power_in Ground reference (0 V) for all voltages referenced in the datasheet.
9 Q7S output Serial data output carrying shift register stage 7 for cascading to the DS input of another device; absolute max output current is ±25 mA.
10 MR input Asynchronous master reset, active LOW; a LOW resets only the shift register and does not affect the storage register.
11 SHCP input Shift register clock; data on DS is shifted in on each LOW-to-HIGH transition of SHCP.
12 STCP input Storage register clock; a LOW-to-HIGH transition transfers the shift register contents to the storage register and parallel outputs.
13 OE input Output enable, active LOW; a HIGH forces the Qn outputs to high-impedance OFF-state without changing the register contents.
14 DS input Serial data input to the shift register stage 0, sampled on the LOW-to-HIGH transition of SHCP.
15 Q0 tri_state Parallel data output Q0 from the storage register; goes to high-impedance OFF-state when OE is HIGH.
16 VCC power_in Supply voltage, recommended range 2.0 V to 6.0 V (absolute maximum 7.0 V).

Key specifications

Parameter Value
Manufacturer HGSEMI
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 5
input clamping current IIK -20 20 mA VI < -0.5V or VI > VCC+0.5V 5
output clamping current IOK -20 20 mA VO < -0.5V or VO > VCC+0.5V 5
output current, pin Q7S IO -25 25 mA VO= -0.5V to (VCC+0.5V) 5
output current, pins Qn IO -35 35 mA VO= -0.5V to (VCC+0.5V) 5
supply current ICC 70 mA 5
ground current IGND -70 mA 5
storage temperature Tstg -65 150 ℃ 5
total power dissipation Ptot 500 mW 5
soldering temperature TL 260 ℃ 10s 5
supply voltage VCC 2 5 6 V 5
input voltage VI 0 V 5
output voltage VO 0 V 5
ambient temperature Tamb -40 85 ℃ 5
HIGH-level input voltage VIH 1.5 1.2 V VCC=2.0V 6
HIGH-level input voltage VIH 3.15 2.4 V VCC=4.5V 6
HIGH-level input voltage VIH 4.2 3.2 V VCC=6.0V 6
LOW-level input voltage VIL 0.8 0.5 V VCC=2.0V 6
LOW-level input voltage VIL 1.35 1 V VCC=4.5V 6
LOW-level input voltage VIL 1.8 1.5 V VCC=6.0V 6
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; all outputs; IO=-20uA; VCC=2.0V 6
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; all outputs; IO=-20uA; VCC=4.5V 6
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; all outputs; IO=-20uA; VCC=6.0V 6
HIGH-level output voltage, Q7S output VOH 3.84 4.32 V VI = VIH or VIL; Q7S output; IO=-4.0mA; VCC=4.5V 6
HIGH-level output voltage, Q7S output VOH 5.34 5.81 V VI = VIH or VIL; Q7S output; IO=-5.2mA; VCC=6.0V 6
HIGH-level output voltage, Qn bus driver outputs VOH 3.84 4.32 V VI = VIH or VIL; Qn bus driver outputs; IO=-6.0mA; VCC=4.5V 6
HIGH-level output voltage, Qn bus driver outputs VOH 5.34 5.81 V VI = VIH or VIL; Qn bus driver outputs; IO=-7.8mA; VCC=6.0V 6
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; all outputs; IO=20uA; VCC=2.0V 6
LOW-level output voltage, Q7S output VOL 0.15 0.33 V VI = VIH or VIL; Q7S output; IO=4.0mA; VCC=4.5V 6
LOW-level output voltage, Q7S output VOL 0.16 0.33 V VI = VIH or VIL; Q7S output; IO=5.2mA; VCC=6.0V 6
LOW-level output voltage, Qn bus driver outputs VOL 0.15 0.33 V VI = VIH or VIL; Qn bus driver outputs; IO=6.0mA; VCC=4.5V 6
LOW-level output voltage, Qn bus driver outputs VOL 0.16 0.33 V VI = VIH or VIL; Qn bus driver outputs; IO=7.8mA; VCC=6.0V 6
input leakage current II -1 1 uA VI=VCC or GND; VCC=6.0V 6
OFF-state output current IOZ -5 5 uA VI=VIH or VIL; VCC=6.0V; VO=VCC or GND 6
supply current ICC 80 uA VI=VCC or GND; IO=0A; VCC=6.0V 6
propagation delay SHCP to Q7S tPLH, tPHL 200 ns VCC=2.0V; see Figure 6 9
propagation delay SHCP to Q7S tPLH, tPHL 40 ns VCC=4.5V; see Figure 6 9
propagation delay SHCP to Q7S tPLH, tPHL 34 ns VCC=6.0V; see Figure 6 9
propagation delay STCP to Qn tPLH, tPHL 220 ns VCC=2.0V; see Figure 7 9
propagation delay STCP to Qn tPLH, tPHL 44 ns VCC=4.5V; see Figure 7 9
propagation delay STCP to Qn tPLH, tPHL 37 ns VCC=6.0V; see Figure 7 9
HIGH to LOW propagation delay MR to Q7S tPHL 220 ns VCC=2.0V; see Figure 9 9
HIGH to LOW propagation delay MR to Q7S tPHL 44 ns VCC=4.5V; see Figure 9 9
HIGH to LOW propagation delay MR to Q7S tPHL 37 ns VCC=6.0V; see Figure 9 9
maximum frequency SHCP or STCP fmax 4.8 MHz VCC=2.0V; see Figure 6 and Figure 7 9
maximum frequency SHCP or STCP fmax 24 MHz VCC=4.5V; see Figure 6 and Figure 7 9
maximum frequency SHCP or STCP fmax 28 MHz VCC=6.0V; see Figure 6 and Figure 7 9
pulse width SHCP HIGH or LOW tW 95 ns VCC=2.0V; see Figure 6 9
pulse width SHCP HIGH or LOW tW 19 ns VCC=4.5V; see Figure 6 9
pulse width SHCP HIGH or LOW tW 16 ns VCC=6.0V; see Figure 6 9
pulse width STCP HIGH or LOW tW 95 ns VCC=2.0V; see Figure 7 9
pulse width STCP HIGH or LOW tW 19 ns VCC=4.5V; see Figure 7 9
pulse width STCP HIGH or LOW tW 16 ns VCC=6.0V; see Figure 7 9
set-up time DS to SHCP tsu 65 ns VCC=2.0V; see Figure 8 9
set-up time DS to SHCP tsu 13 ns VCC=4.5V; see Figure 8 9
set-up time DS to SHCP tsu 11 ns VCC=6.0V; see Figure 8 9

CAD (KiCad official)

  • Symbol: 74HC595DM
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc595dm-etched.step / 74hc595dm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc595dm.step / 74hc595dm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (18 pp, sha256 efeb57a06d16885c, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF