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74HC595BQ

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Nexperia Shift Registers, DHVQFN-16-EP(2.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC595BQ

Nexperia · Shift Registers · DHVQFN-16-EP(2.5x3.5)

74HC595BQ from Nexperia, in a DHVQFN-16-EP(2.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 tri_state Parallel data output Q1; goes high-impedance when OE is HIGH.
2 Q2 tri_state Parallel data output Q2; goes high-impedance when OE is HIGH.
3 Q3 tri_state Parallel data output Q3; goes high-impedance when OE is HIGH.
4 Q4 tri_state Parallel data output Q4; goes high-impedance when OE is HIGH.
5 Q5 tri_state Parallel data output Q5; goes high-impedance when OE is HIGH.
6 Q6 tri_state Parallel data output Q6; goes high-impedance when OE is HIGH.
7 Q7 tri_state Parallel data output Q7; goes high-impedance when OE is HIGH.
8 GND power_in Ground (0 V) reference for all voltages on the device.
9 Q7S output Serial data output used to cascade devices; it is not controlled by OE.
10 MR input Master reset, active LOW; a LOW clears only the shift register and does not affect the storage register.
11 SHCP input Shift register clock; data is shifted in on LOW-to-HIGH transitions.
12 STCP input Storage register clock; a LOW-to-HIGH transition transfers the shift register contents to the storage register.
13 OE input Output enable, active LOW; a HIGH forces Qn outputs to high-impedance without changing register contents.
14 DS input Serial data input to shift register stage 0.
15 Q0 tri_state Parallel data output Q0; goes high-impedance when OE is HIGH.
16 VCC power_in Supply voltage: 2.0 V to 6.0 V for 74HC595 (4.5 V to 5.5 V for 74HCT595) per recommended operating conditions.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Nexperia
Package DHVQFN-16-EP(2.5x3.5)
Category Logic
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 6
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 6
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 6
output current pin Q7S IO -25 25 mA VO = -0.5 V to (VCC + 0.5 V); pin Q7S 6
output current pins Qn IO -35 35 mA VO = -0.5 V to (VCC + 0.5 V); pins Qn 6
supply current ICC 70 mA 6
ground current IGND -70 mA 6
storage temperature Tstg -65 150 °C 6
total power dissipation Ptot 500 mW SOT109-1; SOT403-1; SOT763-1 6
supply voltage VCC 2 5 6 V 7
input voltage VI 0 V 7
output voltage VO 0 V 7
input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 7
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 7
input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 7
ambient temperature Tamb -40 25 125 °C 7
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V; -40 °C to +125 °C 7
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V; -40 °C to +125 °C 7
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V; -40 °C to +125 °C 7
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V; -40 °C to +125 °C 7
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V; -40 °C to +125 °C 7
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V; -40 °C to +125 °C 7
HIGH-level output voltage, all outputs VOH 1.9 2 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; -40 °C to +125 °C 7
HIGH-level output voltage, all outputs VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +125 °C 7
HIGH-level output voltage, all outputs VOH 5.9 6 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; -40 °C to +125 °C 7
HIGH-level output voltage, Q7S output VOH 3.7 4.32 V VI = VIH or VIL; IO = -4 mA; VCC = 4.5 V; -40 °C to +125 °C 7
HIGH-level output voltage, Q7S output VOH 5.2 5.81 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; -40 °C to +125 °C 7
HIGH-level output voltage, Qn bus driver outputs VOH 3.7 4.32 V VI = VIH or VIL; IO = -6 mA; VCC = 4.5 V; -40 °C to +125 °C 7
HIGH-level output voltage, Qn bus driver outputs VOH 5.2 5.81 V VI = VIH or VIL; IO = -7.8 mA; VCC = 6.0 V; -40 °C to +125 °C 7
LOW-level output voltage, all outputs VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C 8
LOW-level output voltage, Q7S output VOL 0.15 0.4 V VI = VIH or VIL; IO = 4 mA; VCC = 4.5 V; -40 °C to +125 °C 8
LOW-level output voltage, Q7S output VOL 0.16 0.4 V VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; -40 °C to +125 °C 8
LOW-level output voltage, Qn bus driver outputs VOL 0.15 0.4 V VI = VIH or VIL; IO = 6 mA; VCC = 4.5 V; -40 °C to +125 °C 8
LOW-level output voltage, Qn bus driver outputs VOL 0.16 0.4 V VI = VIH or VIL; IO = 7.8 mA; VCC = 6.0 V; -40 °C to +125 °C 8
input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C 8
OFF-state output current IOZ -10 10 μA VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND; -40 °C to +125 °C 8
supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C 8
propagation delay SHCP to Q7S tpd 52 240 ns SHCP to Q7S; see Fig. 6; VCC = 2 V; -40 °C to +125 °C 9
propagation delay SHCP to Q7S tpd 19 48 ns SHCP to Q7S; see Fig. 6; VCC = 4.5 V; -40 °C to +125 °C 9
propagation delay SHCP to Q7S tpd 15 41 ns SHCP to Q7S; see Fig. 6; VCC = 6 V; -40 °C to +125 °C 9
propagation delay STCP to Qn tpd 55 265 ns STCP to Qn; see Fig. 7; VCC = 2 V; -40 °C to +125 °C 9
propagation delay STCP to Qn tpd 20 53 ns STCP to Qn; see Fig. 7; VCC = 4.5 V; -40 °C to +125 °C 9
propagation delay STCP to Qn tpd 16 45 ns STCP to Qn; see Fig. 7; VCC = 6 V; -40 °C to +125 °C 9
HIGH to LOW propagation delay MR to Q7S tPHL 47 265 ns MR to Q7S; see Fig. 9; VCC = 2 V; -40 °C to +125 °C 9
HIGH to LOW propagation delay MR to Q7S tPHL 17 53 ns MR to Q7S; see Fig. 9; VCC = 4.5 V; -40 °C to +125 °C 9
HIGH to LOW propagation delay MR to Q7S tPHL 14 45 ns MR to Q7S; see Fig. 9; VCC = 6 V; -40 °C to +125 °C 9
enable time OE to Qn ten 47 225 ns OE to Qn; see Fig. 10; VCC = 2 V; -40 °C to +125 °C 9
enable time OE to Qn ten 17 45 ns OE to Qn; see Fig. 10; VCC = 4.5 V; -40 °C to +125 °C 9
enable time OE to Qn ten 14 38 ns OE to Qn; see Fig. 10; VCC = 6 V; -40 °C to +125 °C 9
disable time OE to Qn tdis 41 225 ns OE to Qn; see Fig. 10; VCC = 2 V; -40 °C to +125 °C 9
disable time OE to Qn tdis 15 45 ns OE to Qn; see Fig. 10; VCC = 4.5 V; -40 °C to +125 °C 9
disable time OE to Qn tdis 12 38 ns OE to Qn; see Fig. 10; VCC = 6 V; -40 °C to +125 °C 9
maximum frequency fmax 4 30 MHz SHCP or STCP; see Fig. 6 and Fig. 7; VCC = 2 V; -40 °C to +125 °C 10
maximum frequency fmax 20 91 MHz SHCP or STCP; see Fig. 6 and Fig. 7; VCC = 4.5 V; -40 °C to +125 °C 10
maximum frequency fmax 24 108 MHz SHCP or STCP; see Fig. 6 and Fig. 7; VCC = 6 V; -40 °C to +125 °C 10
set-up time DS to SHCP tsu 75 11 ns DS to SHCP; see Fig. 8; VCC = 2 V; -40 °C to +125 °C 10
set-up time DS to SHCP tsu 15 4 ns DS to SHCP; see Fig. 8; VCC = 4.5 V; -40 °C to +125 °C 10
set-up time DS to SHCP tsu 13 3 ns DS to SHCP; see Fig. 8; VCC = 6 V; -40 °C to +125 °C 10

CAD (KiCad official)

  • Symbol: 74HC595BQ
  • Footprint: Package_DFN_QFN:DHVQFN-16-1EP_2.5x3.5mm_P0.5mm_EP1x2mm
  • 3D model: DHVQFN-16-EP(2.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 74hc595bq-etched.step / 74hc595bq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc595bq.step / 74hc595bq.glb are the bare package body.

Courtyard: why each corner steps twice

The footprint's courtyard (F.CrtYd, from KiCad's footprint generator) is the union of three rectangles, each grown by 0.25 mm. The body itself is a plain 2.5 x 3.5 mm rectangle (the F.Fab outline).

To see it, switch on the Fab (F.Fab) and Courtyard layers in the PCB Footprint viewer above. The body rectangle's corners stick out past both pad groups, and the courtyard wraps each one.

Feature x extent (mm) y extent (mm)
Side pad rows (pins 2-7, 10-15) +/-1.85 +/-1.625
Package body, 2.5 x 3.5 +/-1.50 +/-2.00
End pads (pins 1, 8, 9, 16) +/-0.625 +/-2.35

The pads overhang the body by 0.35 mm on all four sides, as QFN toe lands do. So the body is wider than the end-pad pair and taller than the side pad rows, and its corner at (1.50, 2.00) lies outside both pad envelopes: the side rows stop at y 1.625, the end pads at x 0.625. Each corner therefore steps side pads (x 1.85) -> body (x 1.50) -> end pads (x 0.625), two steps. The union is 20 vertices and matches the footprint's 20 courtyard segments exactly.

A pads-only outline has one step per corner (12 vertices) but leaves the body corner uncovered. A single step per corner is only possible by growing the courtyard about 0.35 x 0.37 mm at each corner: either the side-pad edge runs down to y 2.0, or the end-pad edge widens to x 1.5. The current outline is the tightest one that covers both body and pads. (Checked 2026-10-16 for the 74HC595 domino molecule, adom/molecule-74hc595bq.)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (21 pp, sha256 fa24207e780cd8c4, retrieved 2026-10-15, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF