74HC595

@@ -3,43 +3,178 @@   "type": "component",   "slug": "74hc595",   "title": "74HC595",-  "brief": "8-bit shift register with output latch, DIP-16 / SOIC-16",+  "brief": "GR Shift Registers, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "74hc595"   ],-  "license": "MIT",   "component": {     "mpn": "74HC595",-    "manufacturer": "Nexperia",-    "package": "DIP-16",-    "pin_count": null,-    "category": "library",-    "subcategory": "",-    "body_size": null,-    "parts": {},-    "distributor_links": {}+    "manufacturer": "GR",+    "package": "SOP-16",+    "pin_count": 16,+    "category": "Logic",+    "subcategory": "Shift Registers",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602886337032962048",+    "parts": {+      "symbol": "74hc595.kicad_sym",+      "footprint": "74hc595.kicad_mod",+      "model_3d": "74hc595.glb",+      "model_3d_step": "74hc595.step",+      "lbr": "74hc595.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "QB",+        "type": "tri_state",+        "description": "Parallel data output bit B (Q1). One of eight 3-state latched parallel outputs; drives typ. 6 mA @ VCC=4.5 V and 7.8 mA @ VCC=6 V."+      },+      {+        "number": "2",+        "name": "QC",+        "type": "tri_state",+        "description": "Parallel data output bit C (Q2). Latched 3-state output; enabled when /G is low, high-Z when /G is high."+      },+      {+        "number": "3",+        "name": "QD",+        "type": "tri_state",+        "description": "Parallel data output bit D (Q3). Latched 3-state output."+      },+      {+        "number": "4",+        "name": "QE",+        "type": "tri_state",+        "description": "Parallel data output bit E (Q4). Latched 3-state output."+      },+      {+        "number": "5",+        "name": "QF",+        "type": "tri_state",+        "description": "Parallel data output bit F (Q5). Latched 3-state output."+      },+      {+        "number": "6",+        "name": "QG",+        "type": "tri_state",+        "description": "Parallel data output bit G (Q6). Latched 3-state output."+      },+      {+        "number": "7",+        "name": "QH",+        "type": "tri_state",+        "description": "Parallel data output bit H (Q7). Latched 3-state output; final stage of the storage register."+      },+      {+        "number": "8",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference (0 V). Absolute-max GND current \u00b170 mA."+      },+      {+        "number": "9",+        "name": "Q'H",+        "type": "output",+        "description": "Serial data output (QH'). Reflects the last stage of the shift register (Qn-1) so multiple 74HC595 devices can be cascaded to build 8n-bit SPI-style parallel outputs. Not 3-state; drives typ. 4 mA @ 4.5 V."+      },+      {+        "number": "10",+        "name": "~SCLR",+        "type": "input",+        "description": "Active-low shift register asynchronous clear. When SCLR = L (with /G low), all shift-register bits are cleared to 0 and Q'H = 0. Must be high for normal shifting."+      },+      {+        "number": "11",+        "name": "SCK",+        "type": "input",+        "description": "Shift-register clock input. On the rising edge, SER is loaded into stage 0 and the shift register advances toward Q'H. Max frequency 10 MHz @ VCC=5 V; min pulse width 20 ns."+      },+      {+        "number": "12",+        "name": "RCK",+        "type": "input",+        "description": "Storage/latch clock (register clock). Rising edge transfers the 8-bit shift-register contents into the output storage latches, which then appear on QA-QH (when /G is low)."+      },+      {+        "number": "13",+        "name": "~G",+        "type": "input",+        "description": "Active-low output enable for the QA-QH 3-state parallel outputs. /G = L drives QA-QH from the latches; /G = H forces QA-QH to high-Z. Does not affect Q'H or the shift-register contents."+      },+      {+        "number": "14",+        "name": "SER",+        "type": "input",+        "description": "Serial data input. Sampled on the rising edge of SCK and shifted into stage 0 of the 8-bit shift register. Setup time 20 ns, hold time 5 ns to SCK."+      },+      {+        "number": "15",+        "name": "QA",+        "type": "tri_state",+        "description": "Parallel data output bit A (Q0). First bit of the 8-bit latched 3-state parallel output; drives typ. 6 mA @ VCC=4.5 V."+      },+      {+        "number": "16",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply, 2 V to 6 V (absolute max \u22120.5 V to 6.5 V). Quiescent ICC \u2264 5 \u00b5A @ VCC = 6 V. Decouple to GND with a local 0.1 \u00b5F capacitor."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602886337032962048",+        "pages": 9,+        "sha256": "16ad2e36da69628c",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 16,+        "described": 16,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }   },-  "readme": "# 74HC595\n\n8-bit shift register with output latch, DIP-16 / SOIC-16\n\nThe 74HC595 is an 8-bit serial-in, parallel-out shift register with output latches. Cascadable for expanding GPIO pins on microcontrollers. One of the most commonly used logic ICs in electronics projects.",+  "metadata": {+    "specs": {+      "Manufacturer": "GR",+      "Package": "SOP-16",+      "Category": "Logic",+      "Pins": "16"+    }+  },+  "variants": [],+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "74hc595"+  ],+  "discovery_pitch": "74HC595 (GR) component page with datasheet-verified CAD.",   "author": {-    "name": "Kyle Bergstedt",-    "email": "[email protected]"+    "name": "Ray",+    "email": "[email protected]"   },-  "visibility": "public",+  "dependencies": {},   "hero": {     "type": "image",     "path": "docs/hero.png"   },-  "sample_prompts": [],-  "discovery_triggers": [],-  "discovery_pitch": null,-  "metadata": {},-  "created_at": "2026-05-28T05:33:12.599Z",-  "updated_at": "2026-05-28T05:33:12.599Z",-  "description": "GR Shift Registers, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",-  "dependencies": {},   "files": [     "page.json",     "README.md",