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74HC594D

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Nexperia Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC594D

Nexperia · Shift Registers · SOIC-16

74HC594D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 output Parallel data output Q1 from the storage register; output current is limited to ±35 mA for parallel outputs Qn (Table 4).
2 Q2 output Parallel data output Q2 from the storage register; output current is limited to ±35 mA for parallel outputs Qn (Table 4).
3 Q3 output Parallel data output Q3 from the storage register; output current is limited to ±35 mA for parallel outputs Qn (Table 4).
4 Q4 output Parallel data output Q4 from the storage register; output current is limited to ±35 mA for parallel outputs Qn (Table 4).
5 Q5 output Parallel data output Q5 from the storage register; output current is limited to ±35 mA for parallel outputs Qn (Table 4).
6 Q6 output Parallel data output Q6 from the storage register; output current is limited to ±35 mA for parallel outputs Qn (Table 4).
7 Q7 output Parallel data output Q7 from the storage register; output current is limited to ±35 mA for parallel outputs Qn (Table 4).
8 GND power_in Ground (0 V) reference for all voltages on the device.
9 Q7S output Serial data output that enables cascading of devices; output current is limited to ±25 mA for Q7S (Table 4).
10 SHR input Shift register reset, active LOW; a LOW level clears the shift register.
11 SHCP input Shift register clock input; data is shifted on each LOW-to-HIGH transition.
12 STCP input Storage register clock input; shift register data is transferred to the storage register and outputs on a LOW-to-HIGH transition.
13 STR input Storage register reset, active LOW; a LOW level clears the storage register.
14 DS input Serial data input loaded into shift register stage 0 on a LOW-to-HIGH SHCP transition while SHR is HIGH; inputs include clamp diodes so current-limiting resistors allow voltages above VCC.
15 Q0 output Parallel data output Q0 from the storage register; output current is limited to ±35 mA for parallel outputs Qn (Table 4).
16 VCC power_in Supply voltage; 2.0 V to 6.0 V for 74HC594 and 4.5 V to 5.5 V for 74HCT594 (Table 5).

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 6
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 6
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 6
Output current serial data output Q7S IO -25 25 mA Q7S; VO = -0.5 V to VCC + 0.5 V 6
Output current parallel data output Qn IO -35 35 mA Qn; VO = -0.5 V to VCC + 0.5 V 6
Supply current serial data output Q7S ICC 50 mA Q7S 6
Supply current parallel data output Qn ICC 70 mA Qn 6
Ground current serial data output Q7S IGND -50 mA Q7S 6
Ground current parallel data output Qn IGND -70 mA Qn 6
Storage temperature Tstg -65 150 °C 6
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 6
Supply voltage VCC 2 5 6 V 74HC594 column 6
Input voltage VI 0 V max printed as VCC 6
Output voltage VO 0 V max printed as VCC 6
Ambient temperature Tamb -40 125 °C 6
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 6
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 6
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 6
HIGH-level input voltage VIH 1.5 V Tamb = -40 °C to +125 °C; VCC = 2.0 V 8
HIGH-level input voltage VIH 3.15 V Tamb = -40 °C to +125 °C; VCC = 4.5 V 8
HIGH-level input voltage VIH 4.2 V Tamb = -40 °C to +125 °C; VCC = 6.0 V 8
LOW-level input voltage VIL 0.5 V Tamb = -40 °C to +125 °C; VCC = 2.0 V 8
LOW-level input voltage VIL 1.35 V Tamb = -40 °C to +125 °C; VCC = 4.5 V 8
LOW-level input voltage VIL 1.8 V Tamb = -40 °C to +125 °C; VCC = 6.0 V 8
HIGH-level output voltage Q7S VOH 3.7 V Tamb = -40 °C to +125 °C; Q7S; IO = -4.0 mA; VCC = 4.5 V; VI = VIH or VIL 8
HIGH-level output voltage Qn VOH 3.7 V Tamb = -40 °C to +125 °C; Qn; IO = -6.0 mA; VCC = 4.5 V; VI = VIH or VIL 8
HIGH-level output voltage Q7S VOH 5.2 V Tamb = -40 °C to +125 °C; Q7S; IO = -5.2 mA; VCC = 6.0 V; VI = VIH or VIL 8
HIGH-level output voltage Qn VOH 5.2 V Tamb = -40 °C to +125 °C; Qn; IO = -7.8 mA; VCC = 6.0 V; VI = VIH or VIL 8
LOW-level output voltage Q7S VOL 0.4 V Tamb = -40 °C to +125 °C; Q7S; IO = 4.0 mA; VCC = 4.5 V; VI = VIH or VIL 8
LOW-level output voltage Qn VOL 0.4 V Tamb = -40 °C to +125 °C; Qn; IO = 6.0 mA; VCC = 4.5 V; VI = VIH or VIL 8
Input leakage current II -1 1 μA Tamb = -40 °C to +125 °C; VI = VCC or GND; VCC = 6.0 V 8
Supply current ICC 160 μA Tamb = -40 °C to +125 °C; VI = VCC or GND; IO = 0 A; VCC = 6.0 V 8
Propagation delay SHCP to Q7S tpd 225 ns Tamb = -40 °C to +125 °C; GND = 0 V; tr = tf = 6 ns; CL = 50 pF; VCC = 2.0 V; see Fig. 6 10
Propagation delay SHCP to Q7S tpd 45 ns Tamb = -40 °C to +125 °C; GND = 0 V; tr = tf = 6 ns; CL = 50 pF; VCC = 4.5 V; see Fig. 6 10
Propagation delay SHCP to Q7S tpd 38 ns Tamb = -40 °C to +125 °C; GND = 0 V; tr = tf = 6 ns; CL = 50 pF; VCC = 6.0 V; see Fig. 6 10
Propagation delay STCP to Qn tpd 225 ns Tamb = -40 °C to +125 °C; GND = 0 V; tr = tf = 6 ns; CL = 50 pF; VCC = 2.0 V; see Fig. 7 10
Propagation delay STCP to Qn tpd 45 ns Tamb = -40 °C to +125 °C; GND = 0 V; tr = tf = 6 ns; CL = 50 pF; VCC = 4.5 V; see Fig. 7 10
Propagation delay STCP to Qn tpd 38 ns Tamb = -40 °C to +125 °C; GND = 0 V; tr = tf = 6 ns; CL = 50 pF; VCC = 6.0 V; see Fig. 7 10
Propagation delay SHR to Q7S tpd 225 ns Tamb = -40 °C to +125 °C; GND = 0 V; tr = tf = 6 ns; CL = 50 pF; VCC = 2.0 V; see Fig. 10 10
Propagation delay SHR to Q7S tpd 45 ns Tamb = -40 °C to +125 °C; GND = 0 V; tr = tf = 6 ns; CL = 50 pF; VCC = 4.5 V; see Fig. 10 10
Propagation delay SHR to Q7S tpd 38 ns Tamb = -40 °C to +125 °C; GND = 0 V; tr = tf = 6 ns; CL = 50 pF; VCC = 6.0 V; see Fig. 10 10
Propagation delay STR to Qn HIGH to LOW tPHL 185 ns Tamb = -40 °C to +125 °C; GND = 0 V; tr = tf = 6 ns; CL = 50 pF; VCC = 2.0 V; see Fig. 11 10
Propagation delay STR to Qn HIGH to LOW tPHL 37 ns Tamb = -40 °C to +125 °C; GND = 0 V; tr = tf = 6 ns; CL = 50 pF; VCC = 4.5 V; see Fig. 11 10
Propagation delay STR to Qn HIGH to LOW tPHL 31 ns Tamb = -40 °C to +125 °C; GND = 0 V; tr = tf = 6 ns; CL = 50 pF; VCC = 6.0 V; see Fig. 11 10
Maximum clock frequency SHCP or STCP fmax 4 MHz Tamb = -40 °C to +125 °C; VCC = 2.0 V; see Fig. 6 and Fig. 7 12
Maximum clock frequency SHCP or STCP fmax 20 MHz Tamb = -40 °C to +125 °C; VCC = 4.5 V; see Fig. 6 and Fig. 7 12
Maximum clock frequency SHCP or STCP fmax 24 MHz Tamb = -40 °C to +125 °C; VCC = 6.0 V; see Fig. 6 and Fig. 7 12
Pulse width SHCP HIGH or LOW tW 120 ns Tamb = -40 °C to +125 °C; VCC = 2.0 V; see Fig. 6 11
Pulse width SHCP HIGH or LOW tW 24 ns Tamb = -40 °C to +125 °C; VCC = 4.5 V; see Fig. 6 11
Pulse width SHCP HIGH or LOW tW 20 ns Tamb = -40 °C to +125 °C; VCC = 6.0 V; see Fig. 6 11
Set-up time DS to SHCP tsu 150 ns Tamb = -40 °C to +125 °C; VCC = 2.0 V; see Fig. 8 11
Set-up time DS to SHCP tsu 30 ns Tamb = -40 °C to +125 °C; VCC = 4.5 V; see Fig. 8 11
Set-up time DS to SHCP tsu 26 ns Tamb = -40 °C to +125 °C; VCC = 6.0 V; see Fig. 8 11
Hold time DS to SHCP th 35 ns Tamb = -40 °C to +125 °C; VCC = 2.0 V; see Fig. 8 11
Hold time DS to SHCP th 7 ns Tamb = -40 °C to +125 °C; VCC = 4.5 V; see Fig. 8 11
Hold time DS to SHCP th 6 ns Tamb = -40 °C to +125 °C; VCC = 6.0 V; see Fig. 8 11

CAD (KiCad official)

  • Symbol: 74HC594D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc594d-etched.step / 74hc594d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc594d.step / 74hc594d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (23 pp, sha256 0d94428470ab60d2, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF