component
74HC574PW
Public Made by Adomby adom
Nexperia Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC574PW
Nexperia · Flip Flops · TSSOP-20
74HC574PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | 3-state output enable input (active LOW); a HIGH on OE forces the outputs to the high-impedance OFF-state without affecting the flip-flop states. |
| 2 | D0 | input | Data input D0, stored on the LOW-to-HIGH CP transition when the set-up and hold time requirements are met. |
| 3 | D1 | input | Data input D1, stored on the LOW-to-HIGH CP transition when the set-up and hold time requirements are met. |
| 4 | D2 | input | Data input D2, stored on the LOW-to-HIGH CP transition when the set-up and hold time requirements are met. |
| 5 | D3 | input | Data input D3, stored on the LOW-to-HIGH CP transition when the set-up and hold time requirements are met. |
| 6 | D4 | input | Data input D4, stored on the LOW-to-HIGH CP transition when the set-up and hold time requirements are met. |
| 7 | D5 | input | Data input D5, stored on the LOW-to-HIGH CP transition when the set-up and hold time requirements are met. |
| 8 | D6 | input | Data input D6, stored on the LOW-to-HIGH CP transition when the set-up and hold time requirements are met. |
| 9 | D7 | input | Data input D7, stored on the LOW-to-HIGH CP transition when the set-up and hold time requirements are met. |
| 10 | GND | power_in | Ground (0 V) reference for all voltages. |
| 11 | CP | input | Clock input; the flip-flops capture their Dn inputs on the LOW-to-HIGH (edge-triggered) transition. |
| 12 | Q7 | tri_state | 3-state flip-flop output Q7, which goes to high-impedance OFF-state when OE is HIGH. |
| 13 | Q6 | tri_state | 3-state flip-flop output Q6, which goes to high-impedance OFF-state when OE is HIGH. |
| 14 | Q5 | tri_state | 3-state flip-flop output Q5, which goes to high-impedance OFF-state when OE is HIGH. |
| 15 | Q4 | tri_state | 3-state flip-flop output Q4, which goes to high-impedance OFF-state when OE is HIGH. |
| 16 | Q3 | tri_state | 3-state flip-flop output Q3, which goes to high-impedance OFF-state when OE is HIGH. |
| 17 | Q2 | tri_state | 3-state flip-flop output Q2, which goes to high-impedance OFF-state when OE is HIGH. |
| 18 | Q1 | tri_state | 3-state flip-flop output Q1, which goes to high-impedance OFF-state when OE is HIGH. |
| 19 | Q0 | tri_state | 3-state flip-flop output Q0, which goes to high-impedance OFF-state when OE is HIGH. |
| 20 | VCC | power_in | Supply voltage; the datasheet recommends 2.0 V to 6.0 V for 74HC574 and 4.5 V to 5.5 V for 74HCT574. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input transition rise and fall rate, VCC = 2.0 V | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 4 | ||
| Input transition rise and fall rate, VCC = 4.5 V | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 4 | |
| Input transition rise and fall rate, VCC = 6.0 V | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 4 | ||
| Supply voltage (74HC574) | VCC | 2 | 5 | 6 | V | 4 | |
| Input voltage | VI | 0 | V | max printed as VCC | 4 | ||
| Output voltage | VO | 0 | V | max printed as VCC | 4 | ||
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 4 | |
| Supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | 4 | ||
| Input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| Output current | IO | -35 | 35 | mA | VO = -0.5 V to (VCC + 0.5 V) | 4 | |
| Supply current | ICC | 70 | mA | 4 | |||
| Ground current | IGND | -70 | mA | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Total power dissipation | Ptot | 500 | mW | [1] SOT360-1 (TSSOP20) derates 10.0 mW/K above 100 °C | 4 | ||
| HIGH-level input voltage, VCC = 2.0 V | VIH | 1.5 | V | -40 °C to +125 °C; VCC = 2.0 V | 5 | ||
| HIGH-level input voltage, VCC = 4.5 V | VIH | 3.15 | V | -40 °C to +125 °C; VCC = 4.5 V | 5 | ||
| HIGH-level input voltage, VCC = 6.0 V | VIH | 4.2 | V | -40 °C to +125 °C; VCC = 6.0 V | 5 | ||
| LOW-level input voltage, VCC = 2.0 V | VIL | 0.5 | V | -40 °C to +125 °C; VCC = 2.0 V | 5 | ||
| LOW-level input voltage, VCC = 4.5 V | VIL | 1.35 | V | -40 °C to +125 °C; VCC = 4.5 V | 5 | ||
| LOW-level input voltage, VCC = 6.0 V | VIL | 1.8 | V | -40 °C to +125 °C; VCC = 6.0 V | 5 | ||
| HIGH-level output voltage, VCC = 2.0 V | VOH | 1.9 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V | 5 | ||
| HIGH-level output voltage, VCC = 4.5 V | VOH | 4.4 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V | 5 | ||
| HIGH-level output voltage, VCC = 6.0 V | VOH | 5.9 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V | 5 | ||
| HIGH-level output voltage, IO = -6.0 mA | VOH | 3.7 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = -6.0 mA; VCC = 4.5 V | 5 | ||
| HIGH-level output voltage, IO = -7.8 mA | VOH | 5.2 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = -7.8 mA; VCC = 6.0 V | 5 | ||
| LOW-level output voltage, VCC = 2.0 V | VOL | 0.1 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V | 5 | ||
| LOW-level output voltage, VCC = 4.5 V | VOL | 0.1 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = 20 μA; VCC = 4.5 V | 5 | ||
| LOW-level output voltage, VCC = 6.0 V | VOL | 0.1 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = 20 μA; VCC = 6.0 V | 5 | ||
| LOW-level output voltage, IO = 6.0 mA | VOL | 0.4 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = 6.0 mA; VCC = 4.5 V | 5 | ||
| LOW-level output voltage, IO = 7.8 mA | VOL | 0.4 | V | -40 °C to +125 °C; VI = VIH or VIL; IO = 7.8 mA; VCC = 6.0 V | 5 | ||
| Input leakage current | II | -1 | 1 | μA | -40 °C to +125 °C; VI = VCC or GND; VCC = 6.0 V | 5 | |
| OFF-state output current | IOZ | -10 | 10 | μA | -40 °C to +125 °C; VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND | 5 | |
| Supply current | ICC | 160 | μA | -40 °C to +125 °C; VI = VCC or GND; IO = 0 A; VCC = 6.0 V | 5 | ||
| Propagation delay CP to Qn, VCC = 2.0 V | tpd | 225 | ns | -40 °C to +125 °C; CP to Qn; CL = 50 pF; VCC = 2.0 V | 7 | ||
| Propagation delay CP to Qn, VCC = 4.5 V | tpd | 45 | ns | -40 °C to +125 °C; CP to Qn; CL = 50 pF; VCC = 4.5 V | 7 | ||
| Propagation delay CP to Qn, VCC = 6.0 V | tpd | 38 | ns | -40 °C to +125 °C; CP to Qn; CL = 50 pF; VCC = 6.0 V | 7 | ||
| Enable time OE to Qn, VCC = 2.0 V | ten | 210 | ns | -40 °C to +125 °C; OE to Qn; CL = 50 pF; VCC = 2.0 V | 7 | ||
| Enable time OE to Qn, VCC = 4.5 V | ten | 42 | ns | -40 °C to +125 °C; OE to Qn; CL = 50 pF; VCC = 4.5 V | 7 | ||
| Enable time OE to Qn, VCC = 6.0 V | ten | 36 | ns | -40 °C to +125 °C; OE to Qn; CL = 50 pF; VCC = 6.0 V | 7 | ||
| Disable time OE to Qn, VCC = 2.0 V | tdis | 190 | ns | -40 °C to +125 °C; OE to Qn; CL = 50 pF; VCC = 2.0 V | 7 | ||
| Disable time OE to Qn, VCC = 4.5 V | tdis | 38 | ns | -40 °C to +125 °C; OE to Qn; CL = 50 pF; VCC = 4.5 V | 7 | ||
| Disable time OE to Qn, VCC = 6.0 V | tdis | 32 | ns | -40 °C to +125 °C; OE to Qn; CL = 50 pF; VCC = 6.0 V | 7 | ||
| Transition time Qn, VCC = 2.0 V | tt | 90 | ns | -40 °C to +125 °C; Qn; CL = 50 pF; VCC = 2.0 V | 7 | ||
| Transition time Qn, VCC = 4.5 V | tt | 18 | ns | -40 °C to +125 °C; Qn; CL = 50 pF; VCC = 4.5 V | 7 | ||
| Transition time Qn, VCC = 6.0 V | tt | 15 | ns | -40 °C to +125 °C; Qn; CL = 50 pF; VCC = 6.0 V | 7 | ||
| Pulse width CP HIGH or LOW, VCC = 2.0 V | tW | 120 | ns | -40 °C to +125 °C; CP HIGH or LOW; see Fig. 6; VCC = 2.0 V | 7 | ||
| Pulse width CP HIGH or LOW, VCC = 4.5 V | tW | 24 | ns | -40 °C to +125 °C; CP HIGH or LOW; see Fig. 6; VCC = 4.5 V | 7 | ||
| Pulse width CP HIGH or LOW, VCC = 6.0 V | tW | 20 | ns | -40 °C to +125 °C; CP HIGH or LOW; see Fig. 6; VCC = 6.0 V | 7 | ||
| Set-up time Dn to CP, VCC = 2.0 V | tsu | 90 | ns | -40 °C to +125 °C; Dn to CP; see Fig. 6; VCC = 2.0 V | 7 | ||
| Set-up time Dn to CP, VCC = 4.5 V | tsu | 18 | ns | -40 °C to +125 °C; Dn to CP; see Fig. 6; VCC = 4.5 V | 7 | ||
| Set-up time Dn to CP, VCC = 6.0 V | tsu | 15 | ns | -40 °C to +125 °C; Dn to CP; see Fig. 6; VCC = 6.0 V | 7 | ||
| Hold time, VCC = 2.0 V | th | 5 | ns | -40 °C to +125 °C; Dn to CP; see Fig. 6; VCC = 2.0 V | 7 | ||
| Hold time, VCC = 4.5 V | th | 5 | ns | -40 °C to +125 °C; Dn to CP; see Fig. 6; VCC = 4.5 V | 7 | ||
| Hold time, VCC = 6.0 V | th | 5 | ns | -40 °C to +125 °C; Dn to CP; see Fig. 6; VCC = 6.0 V | 7 | ||
| Maximum frequency CP, VCC = 2.0 V | fmax | 4 | MHz | -40 °C to +125 °C; CP; see Fig. 5; VCC = 2.0 V | 7 | ||
| Maximum frequency CP, VCC = 4.5 V | fmax | 20 | MHz | -40 °C to +125 °C; CP; see Fig. 5; VCC = 4.5 V | 7 | ||
| Maximum frequency CP, VCC = 6.0 V | fmax | 24 | MHz | -40 °C to +125 °C; CP; see Fig. 5; VCC = 6.0 V | 7 |
CAD (KiCad official)
- Symbol:
74HC574PW - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
74hc574pw-etched.step/74hc574pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc574pw.step/74hc574pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (17 pp, sha256
2cb7f0c355e59666, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).