component
74HC540D
Public Made by Adomby adom
Nexperia Buffers, Drivers, Receivers, Transceivers, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC540D
Nexperia · Buffers, Drivers, Receivers, Transceivers · SOIC-20-300mil
74HC540D from Nexperia, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE1 | input | Output enable 1, active LOW; a HIGH on OE1 causes outputs Y0 to Y7 to assume the high-impedance OFF-state. |
| 2 | A0 | input | Data input A0 of the inverting buffer; clamp diodes permit current-limited resistors to interface this input to voltages above VCC. |
| 3 | A1 | input | Data input A1 of the inverting buffer; clamp diodes permit current-limited resistors to interface this input to voltages above VCC. |
| 4 | A2 | input | Data input A2 of the inverting buffer; clamp diodes permit current-limited resistors to interface this input to voltages above VCC. |
| 5 | A3 | input | Data input A3 of the inverting buffer; clamp diodes permit current-limited resistors to interface this input to voltages above VCC. |
| 6 | A4 | input | Data input A4 of the inverting buffer; clamp diodes permit current-limited resistors to interface this input to voltages above VCC. |
| 7 | A5 | input | Data input A5 of the inverting buffer; clamp diodes permit current-limited resistors to interface this input to voltages above VCC. |
| 8 | A6 | input | Data input A6 of the inverting buffer; clamp diodes permit current-limited resistors to interface this input to voltages above VCC. |
| 9 | A7 | input | Data input A7 of the inverting buffer; clamp diodes permit current-limited resistors to interface this input to voltages above VCC. |
| 10 | GND | power_in | Ground, 0 V reference for all voltages on the device. |
| 11 | Y7 | tri_state | Inverting 3-state data output Y7 (complement of A7); high-impedance when OE1 or OE2 is HIGH, output current limited to ±35 mA. |
| 12 | Y6 | tri_state | Inverting 3-state data output Y6 (complement of A6); high-impedance when OE1 or OE2 is HIGH, output current limited to ±35 mA. |
| 13 | Y5 | tri_state | Inverting 3-state data output Y5 (complement of A5); high-impedance when OE1 or OE2 is HIGH, output current limited to ±35 mA. |
| 14 | Y4 | tri_state | Inverting 3-state data output Y4 (complement of A4); high-impedance when OE1 or OE2 is HIGH, output current limited to ±35 mA. |
| 15 | Y3 | tri_state | Inverting 3-state data output Y3 (complement of A3); high-impedance when OE1 or OE2 is HIGH, output current limited to ±35 mA. |
| 16 | Y2 | tri_state | Inverting 3-state data output Y2 (complement of A2); high-impedance when OE1 or OE2 is HIGH, output current limited to ±35 mA. |
| 17 | Y1 | tri_state | Inverting 3-state data output Y1 (complement of A1); high-impedance when OE1 or OE2 is HIGH, output current limited to ±35 mA. |
| 18 | Y0 | tri_state | Inverting 3-state data output Y0 (complement of A0); high-impedance when OE1 or OE2 is HIGH, output current limited to ±35 mA. |
| 19 | OE2 | input | Output enable 2, active LOW; a HIGH on OE2 causes outputs Y0 to Y7 to assume the high-impedance OFF-state. |
| 20 | VCC | power_in | Supply voltage: 2.0 V to 6.0 V for 74HC540 and 4.5 V to 5.5 V for 74HCT540 (recommended operating conditions). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-20-300mil |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | 2 | 5 | 6 | V | 5 | |
| input voltage | VI | 0 | V | 5 | |||
| output voltage | VO | 0 | V | 5 | |||
| ambient temperature | Tamb | -40 | 25 | 125 | °C | 5 | |
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 5 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 5 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 5 | ||
| supply voltage | VCC | -0.5 | 7 | V | 5 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 5 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 5 | |
| output current | IO | -35 | 35 | mA | -0.5 V < VO < VCC + 0.5 V | 5 | |
| supply current | ICC | 70 | mA | 5 | |||
| ground current | IGND | -70 | mA | 5 | |||
| storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| total power dissipation | Ptot | 500 | mW | SOT163-1 (SO20): derates 12.3 mW/K above 109 °C | 5 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC = 2.0 V; min over -40 °C to +125 °C | 6 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC = 4.5 V; min over -40 °C to +125 °C | 6 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC = 6.0 V; min over -40 °C to +125 °C | 6 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC = 2.0 V; max over -40 °C to +125 °C | 6 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC = 4.5 V; max over -40 °C to +125 °C | 6 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC = 6.0 V; max over -40 °C to +125 °C | 6 | |
| HIGH-level output voltage | VOH | 1.9 | 2 | V | IO = -20 μA; VCC = 2.0 V; VI = VIH or VIL; min over -40 °C to +125 °C | 6 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | IO = -20 μA; VCC = 4.5 V; VI = VIH or VIL; min over -40 °C to +125 °C | 6 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | IO = -20 μA; VCC = 6.0 V; VI = VIH or VIL; min over -40 °C to +125 °C | 6 | |
| HIGH-level output voltage | VOH | 3.7 | 4.32 | V | IO = -6.0 mA; VCC = 4.5 V; VI = VIH or VIL; min over -40 °C to +125 °C | 6 | |
| HIGH-level output voltage | VOH | 5.2 | 5.81 | V | IO = -7.8 mA; VCC = 6.0 V; VI = VIH or VIL; min over -40 °C to +125 °C | 6 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | IO = 20 μA; VCC = 2.0 V; VI = VIH or VIL; max over -40 °C to +125 °C | 6 | |
| LOW-level output voltage | VOL | 0.15 | 0.4 | V | IO = 6.0 mA; VCC = 4.5 V; VI = VIH or VIL; max over -40 °C to +125 °C | 6 | |
| LOW-level output voltage | VOL | 0.16 | 0.4 | V | IO = 7.8 mA; VCC = 6.0 V; VI = VIH or VIL; max over -40 °C to +125 °C | 6 | |
| input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 6 | |
| OFF-state output current | IOZ | -10 | 10 | μA | VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND; -40 °C to +125 °C | 6 | |
| supply current | ICC | 160 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 6 | ||
| propagation delay An to Yn | tpd | 30 | 150 | ns | CL = 50 pF; VCC = 2.0 V; max over -40 °C to +125 °C; see Fig. 5 | 7 | |
| propagation delay An to Yn | tpd | 11 | 30 | ns | CL = 50 pF; VCC = 4.5 V; max over -40 °C to +125 °C; see Fig. 5 | 7 | |
| propagation delay An to Yn | tpd | 9 | 26 | ns | CL = 50 pF; VCC = 6.0 V; max over -40 °C to +125 °C; see Fig. 5 | 7 | |
| enable time OEn to Yn | ten | 52 | 240 | ns | CL = 50 pF; VCC = 2.0 V; max over -40 °C to +125 °C; see Fig. 6 | 7 | |
| enable time OEn to Yn | ten | 19 | 48 | ns | CL = 50 pF; VCC = 4.5 V; max over -40 °C to +125 °C; see Fig. 6 | 7 | |
| enable time OEn to Yn | ten | 15 | 41 | ns | CL = 50 pF; VCC = 6.0 V; max over -40 °C to +125 °C; see Fig. 6 | 7 | |
| disable time OEn to Yn | tdis | 61 | 240 | ns | CL = 50 pF; VCC = 2.0 V; max over -40 °C to +125 °C; see Fig. 6 | 7 | |
| disable time OEn to Yn | tdis | 22 | 48 | ns | CL = 50 pF; VCC = 4.5 V; max over -40 °C to +125 °C; see Fig. 6 | 7 | |
| disable time OEn to Yn | tdis | 18 | 41 | ns | CL = 50 pF; VCC = 6.0 V; max over -40 °C to +125 °C; see Fig. 6 | 7 | |
| transition time | tt | 14 | 90 | ns | CL = 50 pF; VCC = 2.0 V; max over -40 °C to +125 °C; see Fig. 5 | 7 | |
| transition time | tt | 5 | 18 | ns | CL = 50 pF; VCC = 4.5 V; max over -40 °C to +125 °C; see Fig. 5 | 7 | |
| transition time | tt | 4 | 15 | ns | CL = 50 pF; VCC = 6.0 V; max over -40 °C to +125 °C; see Fig. 5 | 7 |
CAD (KiCad official)
- Symbol:
74HC540D - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
74hc540d-etched.step/74hc540d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc540d.step/74hc540d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (16 pp, sha256
362e8dff06e2d72f, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).