component
74HC423D
Public Made by Adomby adom
Nexperia Monostable Multivibrators, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC423D
Nexperia · Monostable Multivibrators · SO-16
74HC423D from Nexperia, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Trigger input, negative-edge triggered, with Schmitt-trigger action. |
| 2 | 1B | input | Trigger input, positive-edge triggered, with Schmitt-trigger action. |
| 3 | 1RD | input | Direct reset, active LOW; it forces 1Q LOW and 1Q HIGH and inhibits triggering while LOW. |
| 4 | ~{1Q} | output | Output, active LOW (inverted pulse output). |
| 5 | 2Q | output | Output, active HIGH. |
| 6 | 2CEXT | passive | External capacitor connection; the datasheet recommends connecting this pin to GND externally for minimum noise generation. |
| 7 | 2REXT/CEXT | passive | External resistor/capacitor connection that sets the basic output pulse width together with pin 6. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages. |
| 9 | 2A | input | Trigger input, negative-edge triggered, with Schmitt-trigger action. |
| 10 | 2B | input | Trigger input, positive-edge triggered, with Schmitt-trigger action. |
| 11 | 2RD | input | Direct reset, active LOW; it forces 2Q LOW and 2Q HIGH and inhibits triggering while LOW. |
| 12 | ~{2Q} | output | Output, active LOW (inverted pulse output). |
| 13 | 1Q | output | Output, active HIGH. |
| 14 | 1CEXT | passive | External capacitor connection; the datasheet recommends connecting this pin to GND externally for minimum noise generation. |
| 15 | 1REXT/CEXT | passive | External resistor/capacitor connection that sets the basic output pulse width together with pin 14. |
| 16 | VCC | power_in | Supply voltage, specified from 2.0 V to 6.0 V (absolute maximum 7 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SO-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| output current | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V; except for pins nREXT/CEXT | 4 | |
| supply current | ICC | 50 | mA | 4 | |||
| ground current | IGND | -50 | mA | 4 | |||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 500 | mW | SO16 and DHVQFN16 packages | 4 | ||
| supply voltage | VCC | 2 | 5 | 6 | V | 5 | |
| input voltage | VI | 0 | V | maximum printed as VCC | 5 | ||
| output voltage | VO | 0 | V | maximum printed as VCC | 5 | ||
| ambient temperature | Tamb | -40 | 125 | °C | 5 | ||
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 5 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 5 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 5 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC = 2.0 V; -40 °C to +125 °C | 5 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC = 4.5 V; -40 °C to +125 °C | 5 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC = 2.0 V; -40 °C to +125 °C | 5 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC = 4.5 V; -40 °C to +125 °C | 5 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| HIGH-level output voltage | VOH | 1.9 | 2 | V | VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; -40 °C to +125 °C | 5 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +125 °C | 5 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| HIGH-level output voltage | VOH | 3.7 | 4.32 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 5 | |
| HIGH-level output voltage | VOH | 5.2 | 5.81 | V | VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C | 5 | |
| LOW-level output voltage | VOL | 0.15 | 0.4 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 5 | |
| LOW-level output voltage | VOL | 0.16 | 0.4 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| supply current | ICC | 160 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 5 | ||
| propagation delay | tpd | 80 | 385 | ns | nA or nB to nQ or nQ; REXT = 5 kΩ; CEXT = 0 pF; see Fig. 5; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| propagation delay | tpd | 29 | 77 | ns | nA or nB to nQ or nQ; REXT = 5 kΩ; CEXT = 0 pF; see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C | 6 | |
| propagation delay | tpd | 23 | 65 | ns | nA or nB to nQ or nQ; REXT = 5 kΩ; CEXT = 0 pF; see Fig. 5; VCC = 6.0 V; -40 °C to +125 °C | 6 | |
| propagation delay | tpd | 66 | 325 | ns | nRD to nQ or nQ; see Fig. 5; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| propagation delay | tpd | 24 | 65 | ns | nRD to nQ or nQ; see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C | 6 | |
| propagation delay | tpd | 19 | 55 | ns | nRD to nQ or nQ; see Fig. 5; VCC = 6.0 V; -40 °C to +125 °C | 6 | |
| transition time | tt | 19 | 110 | ns | see Fig. 5; VCC = 2.0 V; -40 °C to +125 °C | 6 | |
| transition time | tt | 7 | 22 | ns | see Fig. 5; VCC = 4.5 V; -40 °C to +125 °C | 6 | |
| transition time | tt | 6 | 19 | ns | see Fig. 5; VCC = 6.0 V; -40 °C to +125 °C | 6 | |
| input pulse width (nA input LOW) | 150 | 11 | ns | nA input LOW; see Fig. 5 and Fig. 6; VCC = 2.0 V; -40 °C to +125 °C | 6 | ||
| input pulse width (nA input LOW) | 30 | 4 | ns | nA input LOW; see Fig. 5 and Fig. 6; VCC = 4.5 V; -40 °C to +125 °C | 6 | ||
| input pulse width (nA input LOW) | 26 | 3 | ns | nA input LOW; see Fig. 5 and Fig. 6; VCC = 6.0 V; -40 °C to +125 °C | 6 | ||
| input pulse width (nB input HIGH) | 150 | 17 | ns | nB input HIGH; see Fig. 5 and Fig. 6; VCC = 2.0 V; -40 °C to +125 °C | 6 | ||
| input pulse width (nB input HIGH) | 30 | 6 | ns | nB input HIGH; see Fig. 5 and Fig. 6; VCC = 4.5 V; -40 °C to +125 °C | 6 | ||
| input pulse width (nB input HIGH) | 26 | 5 | ns | nB input HIGH; see Fig. 5 and Fig. 6; VCC = 6.0 V; -40 °C to +125 °C | 6 | ||
| input pulse width (nRD input LOW) | 150 | 14 | ns | nRD input LOW; see Fig. 5 and Fig. 6; VCC = 2.0 V; -40 °C to +125 °C | 6 | ||
| input pulse width (nRD input LOW) | 30 | 5 | ns | nRD input LOW; see Fig. 5 and Fig. 6; VCC = 4.5 V; -40 °C to +125 °C | 6 | ||
| input pulse width (nRD input LOW) | 26 | 4 | ns | nRD input LOW; see Fig. 5 and Fig. 6; VCC = 6.0 V; -40 °C to +125 °C | 6 | ||
| external timing resistor REXT | REXT | 10 | 1000 | kΩ | VCC = 2.0 V; see Fig. 6 | 6 | |
| external timing resistor REXT | REXT | 2 | 1000 | kΩ | VCC = 5.0 V | 6 |
CAD (KiCad official)
- Symbol:
74HC423D - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files:
74hc423d-etched.step/74hc423d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc423d.step/74hc423d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (17 pp, sha256
816f817e1c27b3c6, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).