component
74HC4094PW-Q100J
Public Made by Adomby adom
Nexperia Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"description": "Nexperia Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"logic",
"74hc4094pw-q100j",
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"component": {
"mpn": "74HC4094PW-Q100J",
"manufacturer": "Nexperia",
"package": "TSSOP-16",
"pin_count": 16,
"category": "Logic",
"subcategory": "Shift Registers",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588907974018404352",
"parts": {
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"lbr": "74hc4094pw-q100j.lbr"
},
"distributor_links": {
"lcsc": "C547050",
"digikey": "1727-1457-2-ND",
"mouser": "771-74HC4094PW-Q100J"
},
"distributor_check": {
"checked_at": "2026-10-18T02:30:49Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "1727-1457-2-ND",
"status": "found",
"lifecycle": "Active"
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"pn": "771-74HC4094PW-Q100J",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "STR",
"type": "input",
"description": "Strobe input; when HIGH, the data in the shift register is transferred to the storage register."
},
{
"number": "2",
"name": "D",
"type": "input",
"description": "Serial data input to the 8-stage shift register, clocked in on the LOW-to-HIGH transitions of CP."
},
{
"number": "3",
"name": "CP",
"type": "input",
"description": "Clock input; data is shifted on LOW-to-HIGH transitions and the storage register is not affected by CP alone."
},
{
"number": "4",
"name": "QP0",
"type": "tri_state",
"description": "Parallel 3-state output of storage register stage 0, high-impedance OFF-state when OE is LOW."
},
{
"number": "5",
"name": "QP1",
"type": "tri_state",
"description": "Parallel 3-state output of storage register stage 1, high-impedance OFF-state when OE is LOW."
},
{
"number": "6",
"name": "QP2",
"type": "tri_state",
"description": "Parallel 3-state output of storage register stage 2, high-impedance OFF-state when OE is LOW."
},
{
"number": "7",
"name": "QP3",
"type": "tri_state",
"description": "Parallel 3-state output of storage register stage 3, high-impedance OFF-state when OE is LOW."
},
{
"number": "8",
"name": "GND",
"type": "power_in",
"description": "Ground supply voltage (0 V reference for all voltages)."
},
{
"number": "9",
"name": "QS1",
"type": "output",
"description": "Serial output that presents shift register stage 7 data on LOW-to-HIGH CP transitions, for cascading with fast clock edges."
},
{
"number": "10",
"name": "QS2",
"type": "output",
"description": "Serial output that presents the same data as QS1 on the next HIGH-to-LOW CP transition, for cascading with slow clock edges."
},
{
"number": "11",
"name": "QP7",
"type": "tri_state",
"description": "Parallel 3-state output of storage register stage 7, high-impedance OFF-state when OE is LOW."
},
{
"number": "12",
"name": "QP6",
"type": "tri_state",
"description": "Parallel 3-state output of storage register stage 6, high-impedance OFF-state when OE is LOW."
},
{
"number": "13",
"name": "QP5",
"type": "tri_state",
"description": "Parallel 3-state output of storage register stage 5, high-impedance OFF-state when OE is LOW."
},
{
"number": "14",
"name": "QP4",
"type": "tri_state",
"description": "Parallel 3-state output of storage register stage 4, high-impedance OFF-state when OE is LOW."
},
{
"number": "15",
"name": "OE",
"type": "input",
"description": "Output enable input; outputs show storage register data when HIGH and go to high-impedance OFF-state when LOW, without affecting the registers."
},
{
"number": "16",
"name": "VCC",
"type": "power_in",
"description": "Supply voltage; 2.0 V to 6.0 V for 74HC4094-Q100 and 4.5 V to 5.5 V for 74HCT4094-Q100 (recommended operating range)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
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"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pin-to-function mapping for the PW (TSSOP16, SOT403-1) package was taken from the pinning diagram in"
],
"pages_sent": 18,
"cost_usd": 0.0885,
"at": "2026-10-18T02:29:26"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588907974018404352",
"pages": 18,
"sha256": "9365a6b13f483263",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
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}