component
74HC4094PW
Public Made by Adomby adom
Nexperia Shift Registers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC4094PW
Nexperia · Shift Registers · TSSOP-16
74HC4094PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STR | input | Strobe input; transfers data from shift register to storage register when HIGH. |
| 2 | D | input | Serial data input to 8-stage shift register. |
| 3 | CP | input | Clock input; shifts data on LOW-to-HIGH transitions. |
| 4 | QP0 | tri_state | Parallel output from storage register stage 0; HIGH-impedance state when OE is LOW. |
| 5 | QP1 | tri_state | Parallel output from storage register stage 1; HIGH-impedance state when OE is LOW. |
| 6 | QP2 | tri_state | Parallel output from storage register stage 2; HIGH-impedance state when OE is LOW. |
| 7 | QP3 | tri_state | Parallel output from storage register stage 3; HIGH-impedance state when OE is LOW. |
| 8 | GND | power_in | Ground (0 V) reference. |
| 9 | QS1 | output | Serial output; available at LOW-to-HIGH clock transition for fast cascading. |
| 10 | QS2 | output | Serial output; available at HIGH-to-LOW clock transition for slow cascading. |
| 11 | QP7 | tri_state | Parallel output from storage register stage 7; HIGH-impedance state when OE is LOW. |
| 12 | QP6 | tri_state | Parallel output from storage register stage 6; HIGH-impedance state when OE is LOW. |
| 13 | QP5 | tri_state | Parallel output from storage register stage 5; HIGH-impedance state when OE is LOW. |
| 14 | QP4 | tri_state | Parallel output from storage register stage 4; HIGH-impedance state when OE is LOW. |
| 15 | OE | input | Output enable input; HIGH enables QP0-QP7 outputs, LOW places outputs in HIGH-impedance state. |
| 16 | VCC | power_in | Positive supply voltage; 2.0 V to 6.0 V recommended for 74HC4094. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
74HC4094PW - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
74hc4094pw-etched.step/74hc4094pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc4094pw.step/74hc4094pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (19 pp, sha256
a8d541aff709a8db, retrieved 2026-09-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).