component
74HC4094DR
Public Made by Adomby adom
lingxingic Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"schema_version": 1,
"type": "component",
"slug": "74hc4094dr",
"title": "74HC4094DR",
"brief": "lingxingic Shift Registers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"logic",
"74hc4094dr",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "74HC4094DR",
"manufacturer": "lingxingic",
"package": "SOP-16",
"pin_count": 16,
"category": "Logic",
"subcategory": "Shift Registers",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603345037782896640",
"parts": {
"symbol": "74hc4094dr.kicad_sym",
"footprint": "74hc4094dr.kicad_mod",
"model_3d": "74hc4094dr-hero.glb",
"model_3d_plain": "74hc4094dr.glb",
"model_3d_step": "74hc4094dr-etched.step",
"model_3d_step_plain": "74hc4094dr.step",
"lbr": "74hc4094dr.lbr"
},
"distributor_links": {
"lcsc": "C22390082"
},
"distributor_check": {
"checked_at": "2026-10-09T23:42:48Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "deferred",
"error": "shared DigiKey quota guard: 514 calls left today"
},
"mouser": {
"pn": null,
"status": "no match"
}
},
"pins": [
{
"number": "1",
"name": "STR",
"type": "input",
"description": "Strobe input: when HIGH, data in each shift register stage is transferred to the storage register."
},
{
"number": "2",
"name": "D",
"type": "input",
"description": "Serial data input to the first shift register stage, sampled on the clock transitions."
},
{
"number": "3",
"name": "CP",
"type": "input",
"description": "Clock input: data is shifted on positive-going clock transitions, with a minimum LOW clock pulse width and maximum clock frequency that depend on VDD (3 V to 15 V)."
},
{
"number": "4",
"name": "QP0",
"type": "tri_state",
"description": "Parallel buffered 3-state output stage 0; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW."
},
{
"number": "5",
"name": "QP1",
"type": "tri_state",
"description": "Parallel buffered 3-state output stage 1; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW."
},
{
"number": "6",
"name": "QP2",
"type": "tri_state",
"description": "Parallel buffered 3-state output stage 2; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW."
},
{
"number": "7",
"name": "QP3",
"type": "tri_state",
"description": "Parallel buffered 3-state output stage 3; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW."
},
{
"number": "8",
"name": "VSS",
"type": "power_in",
"description": "Ground (0 V) reference for the supply; the recommended VDD range is 3 V to 15 V referenced to VSS."
},
{
"number": "9",
"name": "QS1",
"type": "output",
"description": "Serial output that presents serial data on positive-going clock edges, for cascading devices in high-speed systems with fast clock rise time."
},
{
"number": "10",
"name": "QS2",
"type": "output",
"description": "Serial output that presents the same serial data on the next negative-going clock edge, for cascading devices when the clock has a slow rise time."
},
{
"number": "11",
"name": "QP7",
"type": "tri_state",
"description": "Parallel buffered 3-state output stage 7; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW."
},
{
"number": "12",
"name": "QP6",
"type": "tri_state",
"description": "Parallel buffered 3-state output stage 6; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW."
},
{
"number": "13",
"name": "QP5",
"type": "tri_state",
"description": "Parallel buffered 3-state output stage 5; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW."
},
{
"number": "14",
"name": "QP4",
"type": "tri_state",
"description": "Parallel buffered 3-state output stage 4; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW."
},
{
"number": "15",
"name": "OE",
"type": "input",
"description": "Output enable input: when HIGH the parallel outputs QP0 to QP7 are enabled; when LOW they are high-impedance."
},
{
"number": "16",
"name": "VDD",
"type": "power_in",
"description": "Supply voltage, recommended range 3 V to 15 V referenced to VSS (absolute maximum 18 V)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The pin configuration (package top-view) drawing in section 2.2 is an image and is not present in th; The ordering table lists 74HC4094DR(LX) without an explicit SOP16 label in the extracted text; the S; Pin 15 is labelled 'OE' with description 'output enable input' in the pin table, and the type was se"
],
"pages_sent": 15,
"cost_usd": 0.061,
"at": "2026-10-09T23:40:40"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603345037782896640",
"pages": 15,
"sha256": "1846a35675616d95",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "74hc4094dr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
9.9,
1.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
"checked": "2026-10-09",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "74hc4094dr-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
9.9,
1.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "d26da9af52aaa5d2bb7c71094bb5bf76ffd53aa268b67b455b8e96c441d79a76",
"checked": "2026-10-09",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "lingxingic",
"Package": "SOP-16",
"Category": "Logic",
"Pins": "16"
}
},
"variants": [],
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"74hc4094dr"
],
"discovery_pitch": "74HC4094DR (lingxingic) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
"author": {
"name": "Ray",
"email": "[email protected]"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"74hc4094dr.kicad_sym",
"74hc4094dr.kicad_mod",
"74hc4094dr.glb",
"74hc4094dr.step",
"74hc4094dr.lbr",
"docs/hero.png",
"docs/74hc4094dr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"74hc4094dr-hero.glb",
"74hc4094dr-hero.overlay.json"
],
"visibility": {
"public": true
}
}