# 74HC4094DR

**lingxingic** · Shift Registers · SOP-16

74HC4094DR from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STR | input | Strobe input: when HIGH, data in each shift register stage is transferred to the storage register. |
| 2 | D | input | Serial data input to the first shift register stage, sampled on the clock transitions. |
| 3 | CP | input | Clock input: data is shifted on positive-going clock transitions, with a minimum LOW clock pulse width and maximum clock frequency that depend on VDD (3 V to 15 V). |
| 4 | QP0 | tri_state | Parallel buffered 3-state output stage 0; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW. |
| 5 | QP1 | tri_state | Parallel buffered 3-state output stage 1; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW. |
| 6 | QP2 | tri_state | Parallel buffered 3-state output stage 2; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW. |
| 7 | QP3 | tri_state | Parallel buffered 3-state output stage 3; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW. |
| 8 | VSS | power_in | Ground (0 V) reference for the supply; the recommended VDD range is 3 V to 15 V referenced to VSS. |
| 9 | QS1 | output | Serial output that presents serial data on positive-going clock edges, for cascading devices in high-speed systems with fast clock rise time. |
| 10 | QS2 | output | Serial output that presents the same serial data on the next negative-going clock edge, for cascading devices when the clock has a slow rise time. |
| 11 | QP7 | tri_state | Parallel buffered 3-state output stage 7; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW. |
| 12 | QP6 | tri_state | Parallel buffered 3-state output stage 6; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW. |
| 13 | QP5 | tri_state | Parallel buffered 3-state output stage 5; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW. |
| 14 | QP4 | tri_state | Parallel buffered 3-state output stage 4; data from storage appears here when OE is HIGH and the output is high-impedance (Z) when OE is LOW. |
| 15 | OE | input | Output enable input: when HIGH the parallel outputs QP0 to QP7 are enabled; when LOW they are high-impedance. |
| 16 | VDD | power_in | Supply voltage, recommended range 3 V to 15 V referenced to VSS (absolute maximum 18 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | SOP-16 |
| Category | Logic |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `74HC4094DR`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files: `74hc4094dr-etched.step` / `74hc4094dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc4094dr.step` / `74hc4094dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [lingxingic datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603345037782896640) (15 pp, sha256 `1846a35675616d95`, retrieved 2026-10-09, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74hc4094dr-datasheet.pdf)