# 74HC4094D

**Nexperia** · Shift Registers · SOIC-16

74HC4094D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | STR | input | Strobe input; data in shift register is transferred to storage register when STR input is HIGH. |
| 2 | D | input | Serial data input to the 8-stage shift register. |
| 3 | CP | input | Clock input; data is shifted on LOW-to-HIGH transitions of CP input. |
| 4 | QP0 | tri_state | Parallel output (stage 0) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |
| 5 | QP1 | tri_state | Parallel output (stage 1) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |
| 6 | QP2 | tri_state | Parallel output (stage 2) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |
| 7 | QP3 | tri_state | Parallel output (stage 3) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |
| 8 | GND | power_in | Ground supply voltage (0 V reference). |
| 9 | QS1 | tri_state | Serial output; data is available on LOW-to-HIGH transitions of CP for cascading with fast clock edges. |
| 10 | QS2 | tri_state | Serial output; data is available on next HIGH-to-LOW transition of CP for cascading with slow clock edges. |
| 11 | QP7 | tri_state | Parallel output (stage 7) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |
| 12 | QP6 | tri_state | Parallel output (stage 6) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |
| 13 | QP5 | tri_state | Parallel output (stage 5) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |
| 14 | QP4 | tri_state | Parallel output (stage 4) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |
| 15 | OE | input | Output enable input; HIGH enables outputs, LOW causes high-impedance OFF-state; does not affect register state. |
| 16 | VCC | power_in | Supply voltage for 74HC4094; recommended range 2.0 to 6.0 V, operating temperature -40 to +125 °C. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `74HC4094D`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files: `74hc4094d-etched.step` / `74hc4094d-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc4094d.step` / `74hc4094d.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8579711935807750144) (19 pp, sha256 `a8d541aff709a8db`, retrieved 2026-09-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74hc4094d-datasheet.pdf)