component
74HC4060PW
Public Made by Adomby adom
Nexperia Logic ICs, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
74HC4060PW
Nexperia · Logic ICs · TSSOP-16
74HC4060PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q11 | output | Buffered counter output Q11, forced LOW by a HIGH level on MR. |
| 2 | Q12 | output | Buffered counter output Q12, forced LOW by a HIGH level on MR. |
| 3 | Q13 | output | Buffered counter output Q13, forced LOW by a HIGH level on MR. |
| 4 | Q5 | output | Buffered counter output Q5, forced LOW by a HIGH level on MR. |
| 5 | Q4 | output | Buffered counter output Q4, forced LOW by a HIGH level on MR. |
| 6 | Q6 | output | Buffered counter output Q6, forced LOW by a HIGH level on MR. |
| 7 | Q3 | output | Buffered counter output Q3, forced LOW by a HIGH level on MR. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 9 | CTC | passive | External capacitor connection for the oscillator; keep floating when the oscillator is replaced by an external clock at RS. |
| 10 | RTC | passive | External resistor connection for the oscillator; keep floating when the oscillator is replaced by an external clock at RS. |
| 11 | RS | input | Clock input and oscillator pin; the counter advances on the HIGH-to-LOW transition of RS. |
| 12 | MR | input | Master reset input, active HIGH; clears all counter stages and forces all outputs LOW independent of other inputs. |
| 13 | Q8 | output | Buffered counter output Q8, forced LOW by a HIGH level on MR. |
| 14 | Q7 | output | Buffered counter output Q7, forced LOW by a HIGH level on MR. |
| 15 | Q9 | output | Buffered counter output Q9, forced LOW by a HIGH level on MR. |
| 16 | VCC | power_in | Supply voltage; recommended 2.0 V to 6.0 V for 74HC4060 and 4.5 V to 5.5 V for 74HCT4060. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-16 |
| Category | Logic ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | 2 | 5 | 6 | V | 5 | |
| ambient temperature | Tamb | -40 | 125 | °C | 5 | ||
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 5 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 5 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 5 | ||
| supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| output current | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 4 | |
| supply current | ICC | 50 | mA | 4 | |||
| ground current | IGND | -50 | mA | 4 | |||
| storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 4 | ||
| HIGH-level input voltage MR | VIH | 1.5 | 1.3 | V | VCC = 2.0 V; Tamb -40 °C to +125 °C | 5 | |
| HIGH-level input voltage MR | VIH | 3.15 | 2.4 | V | VCC = 4.5 V; Tamb -40 °C to +125 °C | 5 | |
| HIGH-level input voltage MR | VIH | 4.2 | 3.1 | V | VCC = 6.0 V; Tamb -40 °C to +125 °C | 5 | |
| HIGH-level input voltage RS | VIH | 1.7 | V | VCC = 2.0 V; Tamb -40 °C to +125 °C | 5 | ||
| HIGH-level input voltage RS | VIH | 3.6 | V | VCC = 4.5 V; Tamb -40 °C to +125 °C | 5 | ||
| HIGH-level input voltage RS | VIH | 4.8 | V | VCC = 6.0 V; Tamb -40 °C to +125 °C | 5 | ||
| LOW-level input voltage MR | VIL | 0.8 | 0.5 | V | VCC = 2.0 V; Tamb -40 °C to +125 °C | 5 | |
| LOW-level input voltage MR | VIL | 2.1 | 1.35 | V | VCC = 4.5 V; Tamb -40 °C to +125 °C | 5 | |
| LOW-level input voltage MR | VIL | 2.8 | 1.8 | V | VCC = 6.0 V; Tamb -40 °C to +125 °C | 5 | |
| LOW-level input voltage RS | VIL | 0.3 | V | VCC = 2.0 V; Tamb -40 °C to +125 °C | 5 | ||
| LOW-level input voltage RS | VIL | 0.9 | V | VCC = 4.5 V; Tamb -40 °C to +125 °C | 5 | ||
| LOW-level input voltage RS | VIL | 1.2 | V | VCC = 6.0 V; Tamb -40 °C to +125 °C | 5 | ||
| HIGH-level output voltage | VOH | 1.9 | 2 | V | VI = VIH or VIL; except RTC output; IO = -20 μA; VCC = 2.0 V; Tamb -40 °C to +125 °C | 6 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; except RTC output; IO = -20 μA; VCC = 4.5 V; Tamb -40 °C to +125 °C | 6 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | VI = VIH or VIL; except RTC output; IO = -20 μA; VCC = 6.0 V; Tamb -40 °C to +125 °C | 6 | |
| HIGH-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; except RTC and CTC outputs; IO = -4.0 mA; VCC = 4.5 V; Tamb -40 °C to +125 °C | 6 | ||
| HIGH-level output voltage | VOH | 5.2 | V | VI = VIH or VIL; except RTC and CTC outputs; IO = -5.2 mA; VCC = 6.0 V; Tamb -40 °C to +125 °C | 6 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; except RTC output; IO = 20 μA; VCC = 2.0 V; Tamb -40 °C to +125 °C | 6 | |
| LOW-level output voltage | VOL | 0.4 | V | VI = VIH or VIL; except RTC and CTC outputs; IO = 4.0 mA; VCC = 4.5 V; Tamb -40 °C to +125 °C | 6 | ||
| input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V; Tamb -40 °C to +125 °C | 7 | |
| supply current | ICC | 160 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; Tamb -40 °C to +125 °C | 7 | ||
| propagation delay RS to Q3 | tpd | 99 | 450 | ns | RS to Q3; see Fig. 6; VCC = 2.0 V; Tamb -40 °C to +125 °C | 8 | |
| propagation delay RS to Q3 | tpd | 36 | 90 | ns | RS to Q3; see Fig. 6; VCC = 4.5 V; Tamb -40 °C to +125 °C | 8 | |
| propagation delay RS to Q3 | tpd | 29 | 77 | ns | RS to Q3; see Fig. 6; VCC = 6.0 V; Tamb -40 °C to +125 °C | 8 | |
| HIGH to LOW propagation delay MR to Qn | tPHL | 55 | 265 | ns | MR to Qn; see Fig. 8; VCC = 2.0 V; Tamb -40 °C to +125 °C | 8 | |
| HIGH to LOW propagation delay MR to Qn | tPHL | 20 | 53 | ns | MR to Qn; see Fig. 8; VCC = 4.5 V; Tamb -40 °C to +125 °C | 8 | |
| HIGH to LOW propagation delay MR to Qn | tPHL | 16 | 45 | ns | MR to Qn; see Fig. 8; VCC = 6.0 V; Tamb -40 °C to +125 °C | 8 | |
| pulse width RS (HIGH or LOW) | tW | 120 | 17 | ns | RS (HIGH or LOW); see Fig. 6; VCC = 2.0 V; Tamb -40 °C to +125 °C | 8 | |
| pulse width RS (HIGH or LOW) | tW | 24 | 6 | ns | RS (HIGH or LOW); see Fig. 6; VCC = 4.5 V; Tamb -40 °C to +125 °C | 8 | |
| pulse width RS (HIGH or LOW) | tW | 20 | 5 | ns | RS (HIGH or LOW); see Fig. 6; VCC = 6.0 V; Tamb -40 °C to +125 °C | 8 | |
| maximum frequency | fmax | 4 | 26 | MHz | RS; see Fig. 6; VCC = 2.0 V; Tamb -40 °C to +125 °C | 9 | |
| maximum frequency | fmax | 20 | 80 | MHz | RS; see Fig. 6; VCC = 4.5 V; Tamb -40 °C to +125 °C | 9 | |
| maximum frequency | fmax | 24 | 95 | MHz | RS; see Fig. 6; VCC = 6.0 V; Tamb -40 °C to +125 °C | 9 | |
| input capacitance | CI | 3.5 | pF | 7 | |||
| total power dissipation derating | Ptot | 8.5 | mW/K | SOT403-1 (TSSOP16): derates linearly above 91 °C | 4 |
CAD (KiCad official)
- Symbol:
74HC4060PW - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
74hc4060pw-etched.step/74hc4060pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc4060pw.step/74hc4060pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (19 pp, sha256
9d9d4fbd139e4a1e, retrieved 2026-10-17, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusoff(skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74HC4060PW
**Nexperia** · Logic ICs · TSSOP-16
74HC4060PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q11 | output | Buffered counter output Q11, forced LOW by a HIGH level on MR. |
| 2 | Q12 | output | Buffered counter output Q12, forced LOW by a HIGH level on MR. |
| 3 | Q13 | output | Buffered counter output Q13, forced LOW by a HIGH level on MR. |
| 4 | Q5 | output | Buffered counter output Q5, forced LOW by a HIGH level on MR. |
| 5 | Q4 | output | Buffered counter output Q4, forced LOW by a HIGH level on MR. |
| 6 | Q6 | output | Buffered counter output Q6, forced LOW by a HIGH level on MR. |
| 7 | Q3 | output | Buffered counter output Q3, forced LOW by a HIGH level on MR. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 9 | CTC | passive | External capacitor connection for the oscillator; keep floating when the oscillator is replaced by an external clock at RS. |
| 10 | RTC | passive | External resistor connection for the oscillator; keep floating when the oscillator is replaced by an external clock at RS. |
| 11 | RS | input | Clock input and oscillator pin; the counter advances on the HIGH-to-LOW transition of RS. |
| 12 | MR | input | Master reset input, active HIGH; clears all counter stages and forces all outputs LOW independent of other inputs. |
| 13 | Q8 | output | Buffered counter output Q8, forced LOW by a HIGH level on MR. |
| 14 | Q7 | output | Buffered counter output Q7, forced LOW by a HIGH level on MR. |
| 15 | Q9 | output | Buffered counter output Q9, forced LOW by a HIGH level on MR. |
| 16 | VCC | power_in | Supply voltage; recommended 2.0 V to 6.0 V for 74HC4060 and 4.5 V to 5.5 V for 74HCT4060. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-16 |
| Category | Logic ICs |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | 2 | 5 | 6 | V | | 5 |
| ambient temperature | Tamb | -40 | | 125 | °C | | 5 |
| input transition rise and fall rate | Δt/ΔV | | | 625 | ns/V | VCC = 2.0 V | 5 |
| input transition rise and fall rate | Δt/ΔV | | 1.67 | 139 | ns/V | VCC = 4.5 V | 5 |
| input transition rise and fall rate | Δt/ΔV | | | 83 | ns/V | VCC = 6.0 V | 5 |
| supply voltage | VCC | -0.5 | | 7 | V | | 4 |
| input clamping current | IIK | -20 | | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 |
| output clamping current | IOK | -20 | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 |
| output current | IO | -25 | | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 4 |
| supply current | ICC | | | 50 | mA | | 4 |
| ground current | IGND | -50 | | | mA | | 4 |
| storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| total power dissipation | Ptot | | | 500 | mW | Tamb = -40 °C to +125 °C | 4 |
| HIGH-level input voltage MR | VIH | 1.5 | 1.3 | | V | VCC = 2.0 V; Tamb -40 °C to +125 °C | 5 |
| HIGH-level input voltage MR | VIH | 3.15 | 2.4 | | V | VCC = 4.5 V; Tamb -40 °C to +125 °C | 5 |
| HIGH-level input voltage MR | VIH | 4.2 | 3.1 | | V | VCC = 6.0 V; Tamb -40 °C to +125 °C | 5 |
| HIGH-level input voltage RS | VIH | 1.7 | | | V | VCC = 2.0 V; Tamb -40 °C to +125 °C | 5 |
| HIGH-level input voltage RS | VIH | 3.6 | | | V | VCC = 4.5 V; Tamb -40 °C to +125 °C | 5 |
| HIGH-level input voltage RS | VIH | 4.8 | | | V | VCC = 6.0 V; Tamb -40 °C to +125 °C | 5 |
| LOW-level input voltage MR | VIL | | 0.8 | 0.5 | V | VCC = 2.0 V; Tamb -40 °C to +125 °C | 5 |
| LOW-level input voltage MR | VIL | | 2.1 | 1.35 | V | VCC = 4.5 V; Tamb -40 °C to +125 °C | 5 |
| LOW-level input voltage MR | VIL | | 2.8 | 1.8 | V | VCC = 6.0 V; Tamb -40 °C to +125 °C | 5 |
| LOW-level input voltage RS | VIL | | | 0.3 | V | VCC = 2.0 V; Tamb -40 °C to +125 °C | 5 |
| LOW-level input voltage RS | VIL | | | 0.9 | V | VCC = 4.5 V; Tamb -40 °C to +125 °C | 5 |
| LOW-level input voltage RS | VIL | | | 1.2 | V | VCC = 6.0 V; Tamb -40 °C to +125 °C | 5 |
| HIGH-level output voltage | VOH | 1.9 | 2 | | V | VI = VIH or VIL; except RTC output; IO = -20 μA; VCC = 2.0 V; Tamb -40 °C to +125 °C | 6 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | | V | VI = VIH or VIL; except RTC output; IO = -20 μA; VCC = 4.5 V; Tamb -40 °C to +125 °C | 6 |
| HIGH-level output voltage | VOH | 5.9 | 6 | | V | VI = VIH or VIL; except RTC output; IO = -20 μA; VCC = 6.0 V; Tamb -40 °C to +125 °C | 6 |
| HIGH-level output voltage | VOH | 3.7 | | | V | VI = VIH or VIL; except RTC and CTC outputs; IO = -4.0 mA; VCC = 4.5 V; Tamb -40 °C to +125 °C | 6 |
| HIGH-level output voltage | VOH | 5.2 | | | V | VI = VIH or VIL; except RTC and CTC outputs; IO = -5.2 mA; VCC = 6.0 V; Tamb -40 °C to +125 °C | 6 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | VI = VIH or VIL; except RTC output; IO = 20 μA; VCC = 2.0 V; Tamb -40 °C to +125 °C | 6 |
| LOW-level output voltage | VOL | | | 0.4 | V | VI = VIH or VIL; except RTC and CTC outputs; IO = 4.0 mA; VCC = 4.5 V; Tamb -40 °C to +125 °C | 6 |
| input leakage current | II | -1 | | 1 | μA | VI = VCC or GND; VCC = 6.0 V; Tamb -40 °C to +125 °C | 7 |
| supply current | ICC | | | 160 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; Tamb -40 °C to +125 °C | 7 |
| propagation delay RS to Q3 | tpd | | 99 | 450 | ns | RS to Q3; see Fig. 6; VCC = 2.0 V; Tamb -40 °C to +125 °C | 8 |
| propagation delay RS to Q3 | tpd | | 36 | 90 | ns | RS to Q3; see Fig. 6; VCC = 4.5 V; Tamb -40 °C to +125 °C | 8 |
| propagation delay RS to Q3 | tpd | | 29 | 77 | ns | RS to Q3; see Fig. 6; VCC = 6.0 V; Tamb -40 °C to +125 °C | 8 |
| HIGH to LOW propagation delay MR to Qn | tPHL | | 55 | 265 | ns | MR to Qn; see Fig. 8; VCC = 2.0 V; Tamb -40 °C to +125 °C | 8 |
| HIGH to LOW propagation delay MR to Qn | tPHL | | 20 | 53 | ns | MR to Qn; see Fig. 8; VCC = 4.5 V; Tamb -40 °C to +125 °C | 8 |
| HIGH to LOW propagation delay MR to Qn | tPHL | | 16 | 45 | ns | MR to Qn; see Fig. 8; VCC = 6.0 V; Tamb -40 °C to +125 °C | 8 |
| pulse width RS (HIGH or LOW) | tW | 120 | 17 | | ns | RS (HIGH or LOW); see Fig. 6; VCC = 2.0 V; Tamb -40 °C to +125 °C | 8 |
| pulse width RS (HIGH or LOW) | tW | 24 | 6 | | ns | RS (HIGH or LOW); see Fig. 6; VCC = 4.5 V; Tamb -40 °C to +125 °C | 8 |
| pulse width RS (HIGH or LOW) | tW | 20 | 5 | | ns | RS (HIGH or LOW); see Fig. 6; VCC = 6.0 V; Tamb -40 °C to +125 °C | 8 |
| maximum frequency | fmax | 4 | 26 | | MHz | RS; see Fig. 6; VCC = 2.0 V; Tamb -40 °C to +125 °C | 9 |
| maximum frequency | fmax | 20 | 80 | | MHz | RS; see Fig. 6; VCC = 4.5 V; Tamb -40 °C to +125 °C | 9 |
| maximum frequency | fmax | 24 | 95 | | MHz | RS; see Fig. 6; VCC = 6.0 V; Tamb -40 °C to +125 °C | 9 |
| input capacitance | CI | | 3.5 | | pF | | 7 |
| total power dissipation derating | Ptot | | 8.5 | | mW/K | SOT403-1 (TSSOP16): derates linearly above 91 °C | 4 |
## CAD (KiCad official)
- Symbol: `74HC4060PW`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `74hc4060pw-etched.step` / `74hc4060pw-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc4060pw.step` / `74hc4060pw.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74HC4060PW.pdf) (19 pp, sha256 `9d9d4fbd139e4a1e`, retrieved 2026-10-17, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `off` (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74hc4060pw-datasheet.pdf)