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74HC4060BQ-Q100

Public Made by Adom

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Nexperia Counters, Dividers, DHVQFN-16-EP(2.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC4060BQ-Q100

Nexperia · Counters, Dividers · DHVQFN-16-EP(2.5x3.5)

74HC4060BQ-Q100 from Nexperia, in a DHVQFN-16-EP(2.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q11 output Buffered counter output Q11 of the 14-stage ripple counter; forced LOW when MR is HIGH.
2 Q12 output Buffered counter output Q12 of the 14-stage ripple counter; forced LOW when MR is HIGH.
3 Q13 output Buffered counter output Q13 of the 14-stage ripple counter; forced LOW when MR is HIGH.
4 Q5 output Buffered counter output Q5 of the 14-stage ripple counter; forced LOW when MR is HIGH.
5 Q4 output Buffered counter output Q4 of the 14-stage ripple counter; forced LOW when MR is HIGH.
6 Q6 output Buffered counter output Q6 of the 14-stage ripple counter; forced LOW when MR is HIGH.
7 Q3 output Buffered counter output Q3 of the 14-stage ripple counter; forced LOW when MR is HIGH.
8 GND power_in Ground (0 V); all voltages are referenced to this pin.
9 CTC passive External capacitor connection for the RC oscillator; Ct must be larger than the inherent stray capacitance with Ct > 50 pF recommended, and the pin is kept floating when RS is driven by an external clock.
10 RTC passive External resistor connection for the RC oscillator; recommended 10 kΩ < Rt < 1 MΩ with Rt ≥ 1 kΩ to avoid start-up problems, and the pin is kept floating when RS is driven by an external clock.
11 RS input Clock input or oscillator pin; the counter advances on the HIGH-to-LOW transition of RS and it may be driven by an external clock.
12 MR input Master reset input, active HIGH; a HIGH level clears all counter stages and forces all outputs LOW independent of other inputs.
13 Q8 output Buffered counter output Q8 of the 14-stage ripple counter; forced LOW when MR is HIGH.
14 Q7 output Buffered counter output Q7 of the 14-stage ripple counter; forced LOW when MR is HIGH.
15 Q9 output Buffered counter output Q9 of the 14-stage ripple counter; forced LOW when MR is HIGH.
16 VCC power_in Supply voltage; recommended range 2.0 V to 6.0 V for 74HC4060-Q100 and 4.5 V to 5.5 V for 74HCT4060-Q100, with absolute maximum of +7 V.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Nexperia
Package DHVQFN-16-EP(2.5x3.5)
Category Logic
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VCC -0.5 7 V 4
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
Output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 4
Supply current (absolute maximum) ICC 50 mA 4
Ground current IGND -50 mA 4
Storage temperature Tstg -65 150 °C 4
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
Supply voltage VCC 2 5 6 V 5
Input voltage VI 0 V 5
Output voltage VO 0 V 5
Ambient temperature Tamb -40 125 °C 5
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 5
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 5
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 5
HIGH-level input voltage (MR input) VIH 1.5 1.3 V VCC = 2.0 V 5
HIGH-level input voltage (MR input) VIH 3.15 2.4 V VCC = 4.5 V 5
HIGH-level input voltage (MR input) VIH 4.2 3.1 V VCC = 6.0 V 5
HIGH-level input voltage (RS input) VIH 1.7 V VCC = 2.0 V 5
HIGH-level input voltage (RS input) VIH 3.6 V VCC = 4.5 V 5
HIGH-level input voltage (RS input) VIH 4.8 V VCC = 6.0 V 5
LOW-level input voltage (MR input) VIL 0.8 0.5 V VCC = 2.0 V 5
LOW-level input voltage (MR input) VIL 2.1 1.35 V VCC = 4.5 V 5
LOW-level input voltage (MR input) VIL 2.8 1.8 V VCC = 6.0 V 5
LOW-level input voltage (RS input) VIL 0.3 V VCC = 2.0 V 5
LOW-level input voltage (RS input) VIL 0.9 V VCC = 4.5 V 5
LOW-level input voltage (RS input) VIL 1.2 V VCC = 6.0 V 5
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V 7
Supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V 7
Propagation delay RS to Q3 tpd 99 450 ns CL = 50 pF; VCC = 2.0 V; see Fig. 6 8
Propagation delay RS to Q3 tpd 36 90 ns CL = 50 pF; VCC = 4.5 V; see Fig. 6 8
Propagation delay RS to Q3 tpd 29 77 ns CL = 50 pF; VCC = 6.0 V; see Fig. 6 8
Propagation delay Qn to Qn+1 tpd 22 120 ns CL = 50 pF; VCC = 2.0 V; see Fig. 7 8
Propagation delay Qn to Qn+1 tpd 8 24 ns CL = 50 pF; VCC = 4.5 V; see Fig. 7 8
Propagation delay Qn to Qn+1 tpd 6 20 ns CL = 50 pF; VCC = 6.0 V; see Fig. 7 8
HIGH to LOW propagation delay MR to Qn tPHL 55 265 ns CL = 50 pF; VCC = 2.0 V; see Fig. 8 8
HIGH to LOW propagation delay MR to Qn tPHL 20 53 ns CL = 50 pF; VCC = 4.5 V; see Fig. 8 8
HIGH to LOW propagation delay MR to Qn tPHL 16 45 ns CL = 50 pF; VCC = 6.0 V; see Fig. 8 8
Maximum frequency RS fmax 4 26 MHz VCC = 2.0 V; see Fig. 6 9
Maximum frequency RS fmax 20 80 MHz VCC = 4.5 V; see Fig. 6 9
Maximum frequency RS fmax 24 95 MHz VCC = 6.0 V; see Fig. 6 9
Recovery time MR to RS trec 150 28 ns VCC = 2.0 V; see Fig. 8 8
Recovery time MR to RS trec 30 10 ns VCC = 4.5 V; see Fig. 8 8
Recovery time MR to RS trec 26 8 ns VCC = 6.0 V; see Fig. 8 8
Pulse width RS (HIGH or LOW) tW 120 17 ns VCC = 2.0 V; see Fig. 6 8
Pulse width RS (HIGH or LOW) tW 24 6 ns VCC = 4.5 V; see Fig. 6 8
Pulse width RS (HIGH or LOW) tW 20 5 ns VCC = 6.0 V; see Fig. 6 8
Pulse width MR (HIGH) tW 120 25 ns VCC = 2.0 V; see Fig. 8 8
Pulse width MR (HIGH) tW 24 9 ns VCC = 4.5 V; see Fig. 8 8
Pulse width MR (HIGH) tW 20 7 ns VCC = 6.0 V; see Fig. 8 8
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; except RTC output; IO = -20 μA; VCC = 2.0 V 6
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; except RTC output; IO = -20 μA; VCC = 4.5 V 6
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; except RTC output; IO = -20 μA; VCC = 6.0 V 6
HIGH-level output voltage VOH 3.7 V VI = VIH or VIL; except RTC and CTC outputs; IO = -4.0 mA; VCC = 4.5 V 6
HIGH-level output voltage VOH 5.2 V VI = VIH or VIL; except RTC and CTC outputs; IO = -5.2 mA; VCC = 6.0 V 6
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; except RTC output; IO = 20 μA; VCC = 2.0 V 6
LOW-level output voltage VOL 0.4 V VI = VIH or VIL; except RTC and CTC outputs; IO = 4.0 mA; VCC = 4.5 V 6

CAD (KiCad official)

  • Symbol: 74HC4060BQ-Q100
  • Footprint: Package_DFN_QFN:DHVQFN-16-1EP_2.5x3.5mm_P0.5mm_EP1x2mm
  • 3D model: DHVQFN-16-EP(2.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: 74hc4060bq-q100-etched.step / 74hc4060bq-q100-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc4060bq-q100.step / 74hc4060bq-q100.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (19 pp, sha256 9e425603fd941f44, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF