# 74HC4053N

**HGSEMI** · Signal Switches, Multiplexers, Decoders · DIP-16

74HC4053N from HGSEMI, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1B | bidirectional | Independent analog input/output Y1B of switch B, passed to common terminal ZB when E is low and SB is high. |
| 2 | Y0B | bidirectional | Independent analog input/output Y0B of switch B, passed to common terminal ZB when E is low and SB is low. |
| 3 | Y1C | bidirectional | Independent analog input/output Y1C of switch C, passed to common terminal ZC when E is low and SC is high. |
| 4 | ZC | bidirectional | Common analog input/output of switch C, connected to Y0C or Y1C selected by SC while E is low; all channels off when E is high. |
| 5 | Y0C | bidirectional | Independent analog input/output Y0C of switch C, passed to common terminal ZC when E is low and SC is low. |
| 6 | E | input | Enable input, active low: when low the selected switch is on, and when high all switches are off regardless of SA, SB and SC. |
| 7 | VEE | power_in | Negative supply voltage; VDD-VEE must stay within 3.0 V to 9.0 V (recommended), and analog I/O may swing down to VEE. |
| 8 | VSS | power_in | Ground, the reference for the digital control inputs SA, SB, SC and E; VSS and VEE are tied together when used as a digital multiplexer. |
| 9 | SC | input | Select input for channel C: low selects Y0C-ZC and high selects Y1C-ZC while E is low. |
| 10 | SB | input | Select input for channel B: low selects Y0B-ZB and high selects Y1B-ZB while E is low. |
| 11 | SA | input | Select input for channel A: low selects Y0A-ZA and high selects Y1A-ZA while E is low; digital input must stay between VSS and VDD. |
| 12 | Y0A | bidirectional | Independent analog input/output Y0A of switch A, passed to common terminal ZA when E is low and SA is low. |
| 13 | Y1A | bidirectional | Independent analog input/output Y1A of switch A, passed to common terminal ZA when E is low and SA is high. |
| 14 | ZA | bidirectional | Common analog input/output of switch A, connected to Y0A or Y1A selected by SA while E is low; all channels off when E is high. |
| 15 | ZB | bidirectional | Common analog input/output of switch B, connected to Y0B or Y1B selected by SB while E is low; all channels off when E is high. |
| 16 | VDD | power_in | Positive supply voltage for the digital control inputs; VDD-VEE is 3.0 V to 9.0 V (recommended) and must not exceed 9 V in normal use (absolute maximum 12 V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VDD | -0.5 |  | 12 | V |  | 5 |
| Supply voltage range (VDD-VEE) | VDD-VEE | -0.5 |  | 12 | V |  | 5 |
| Static current | IQ |  |  | 2 | μA | VDD-VEE=12V | 5 |
| Input voltage range | VI | -0.5 |  |  | V |  | 5 |
| High-level input current | /IIH/ |  |  | 1 | μA | VDD=5V, VI=VDD | 5 |
| Low-level input current | /IIL/ |  |  | 1 | μA | VDD=5V, VI=0V | 5 |
| Input clamp current | IIK | -20 |  | 20 | mA | VI<-0.5V or VI>VDD+0.5V | 5 |
| Input-output clamp current | IIOK | -20 |  | 20 | mA | VIO<VEE-0.5V or VIO>VDD+0.5V | 5 |
| Switch on-state current | IT | -25 |  | 25 | mA | VO=-0.5V~VDD+0.5V | 5 |
| VDD or GND current | IDD, IGND | -50 |  | 50 | mA |  | 5 |
| Power dissipation | PD |  |  | 500 | mW |  | 5 |
| Storage temperature | TSTG | -65 |  | 150 | ℃ |  | 5 |
| Operating temperature (absolute maximum table) | TOP | -40 |  | 85 | ℃ |  | 5 |
| Soldering temperature | TL |  |  | 260 | ℃ | 10 s | 5 |
| Supply voltage | VDD | 3 | 5 | 9 | V |  | 5 |
| Supply voltage | VEE | -6 |  | 0 | V |  | 5 |
| Supply voltage (VDD-VEE) | VDD-VEE | 3 |  | 9 | V |  | 5 |
| Input voltage | VI | 0 |  |  | V |  | 5 |
| Input rise/fall time | tr,tf |  |  | 1000 | ns | VCC=3.0V | 5 |
| Input rise/fall time | tr,tf |  |  | 500 | ns | VCC=5.0V | 5 |
| Input rise/fall time | tr,tf |  |  | 400 | ns | VCC=6.0V | 5 |
| Operating temperature | TOP | -40 |  | 85 | ℃ |  | 5 |
| On-state resistance (Vis=0~VDD-VEE) | RON |  | 350 | 2500 | Ω | VDD-VEE=5V; Vis=0～VDD－VEE; 见图1 | 6 |
| On-state resistance (Vis=0~VDD-VEE) | RON |  | 80 | 245 | Ω | VDD-VEE=9V; Vis=0～VDD－VEE; 见图1 | 6 |
| On-state resistance (Vis=0) | RON |  | 115 | 340 | Ω | VDD-VEE=5V; Vis=0; 见图1 | 6 |
| On-state resistance (Vis=0) | RON |  | 50 | 160 | Ω | VDD-VEE=9V; Vis=0; 见图1 | 6 |
| On-state resistance (Vis=VDD-VEE) | RON |  | 120 | 365 | Ω | VDD-VEE=5V; Vis=VDD－VEE; 见图1 | 6 |
| On-state resistance (Vis=VDD-VEE) | RON |  | 65 | 200 | Ω | VDD-VEE=9V; Vis=VDD－VEE; 见图1 | 6 |
| Off-state leakage current (all channels off) | IOZZ |  |  | 1000 | nA | VDD-VEE=9V; 所有通道关断; ￾ 处于VDD | 6 |
| Off-state leakage current (any channel) | IOZY |  |  | 200 | nA | VDD-VEE=9V; 任一通道; ￾ 处于VEE | 6 |
| Propagation delay Vis→Vos, high to low | tPHL |  | 10 | 20 | ns | VDD=5V; 注释 1 | 7 |
| Propagation delay Vis→Vos, high to low | tPHL |  | 5 | 10 | ns | VDD=9V; 注释 1 | 7 |
| Propagation delay Vis→Vos, low to high | tPLH |  | 15 | 30 | ns | VDD=5V; 注释 1 | 7 |
| Propagation delay Vis→Vos, low to high | tPLH |  | 5 | 10 | ns | VDD=9V; 注释 1 | 7 |
| Propagation delay An→Vos, high to low | tPHL |  | 200 | 400 | ns | VDD=5V; 注释 2 | 7 |
| Propagation delay An→Vos, high to low | tPHL |  | 85 | 170 | ns | VDD=9V; 注释 2 | 7 |
| Propagation delay An→Vos, low to high | tPLH |  | 275 | 555 | ns | VDD=5V; 注释 2 | 7 |
| Propagation delay An→Vos, low to high | tPLH |  | 100 | 200 | ns | VDD=9V; 注释 2 | 7 |
| Output disable time high (to Z) | tPHZ |  | 200 | 400 | ns | VDD=5V; 注释 3 | 7 |
| Output disable time high (to Z) | tPHZ |  | 115 | 230 | ns | VDD=9V; 注释 3 | 7 |
| Output disable time low (to Z) | tPLZ |  | 200 | 400 | ns | VDD=5V; 注释 3 | 7 |
| Output disable time low (to Z) | tPLZ |  | 120 | 245 | ns | VDD=9V; 注释 3 | 7 |
| Output enable time high (from Z) | tPZH |  | 260 | 525 | ns | VDD=5V; 注释 3 | 8 |
| Output enable time high (from Z) | tPZH |  | 95 | 190 | ns | VDD=9V; 注释 3 | 8 |
| Output enable time low (from Z) | tPZL |  | 280 | 565 | ns | VDD=5V; 注释 3 | 8 |
| Output enable time low (from Z) | tPZL |  | 105 | 205 | ns | VDD=9V; 注释 3 | 8 |
| Distortion (sine wave response) |  |  |  | 0.25 | % | VDD=5V; 注释 4 | 8 |
| Distortion (sine wave response) |  |  |  | 0.04 | % | VDD=9V; 注释 4 | 8 |
| Crosstalk, enable or select to output |  |  |  | 50 | mV | 注释 6 | 8 |

## CAD (KiCad official)

- Symbol: `74HC4053N`
- Footprint: `Package_DIP:DIP-16_W7.62mm`
- 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files: `74hc4053n-etched.step` / `74hc4053n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc4053n.step` / `74hc4053n.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HGSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8757117155840409600) (14 pp, sha256 `6251001d9d3adc12`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74hc4053n-datasheet.pdf)