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74HC4053DRG

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HANSCHIP semiconductor Analog Switches, Multiplexers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC4053DRG

HANSCHIP semiconductor · Analog Switches, Multiplexers · SOP-16

74HC4053DRG from HANSCHIP semiconductor, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Y1B passive Independent analog input/output of switch B (Y1B), connected to common ZB when SB is high and enable is low; analog levels must stay between VEE and VDD.
2 Y0B passive Independent analog input/output of switch B (Y0B), connected to common ZB when SB is low and enable is low; analog levels must stay between VEE and VDD.
3 Y1C passive Independent analog input/output of switch C (Y1C), connected to common ZC when SC is high and enable is low; analog levels must stay between VEE and VDD.
4 ZC passive Common analog input/output of switch C, connected to Y0C or Y1C according to SC while enable is low; analog levels must stay between VEE and VDD.
5 Y0C passive Independent analog input/output of switch C (Y0C), connected to common ZC when SC is low and enable is low; analog levels must stay between VEE and VDD.
6 E input Active-low enable input; when high, all switches are off in high-impedance state regardless of SA, SB and SC.
7 VEE power_in Negative supply voltage, recommended range -6.0 V to 0 V, with VDD-VEE between 3.0 V and 9.0 V (not to exceed 9 V).
8 VSS power_in Ground pin supplying the digital control inputs; VEE and VSS are tied together (usually grounded) when the device is used as a digital multiplexer.
9 SC input Channel C select input: low selects Y0C to ZC and high selects Y1C to ZC when enable is low; input range 0 to VDD.
10 SB input Channel B select input: low selects Y0B to ZB and high selects Y1B to ZB when enable is low; input range 0 to VDD.
11 SA input Channel A select input: low selects Y0A to ZA and high selects Y1A to ZA when enable is low; input range 0 to VDD.
12 Y0A passive Independent analog input/output of switch A (Y0A), connected to common ZA when SA is low and enable is low; analog levels must stay between VEE and VDD.
13 Y1A passive Independent analog input/output of switch A (Y1A), connected to common ZA when SA is high and enable is low; analog levels must stay between VEE and VDD.
14 ZA passive Common analog input/output of switch A, connected to Y0A or Y1A according to SA while enable is low; analog levels must stay between VEE and VDD.
15 ZB passive Common analog input/output of switch B, connected to Y0B or Y1B according to SB while enable is low; analog levels must stay between VEE and VDD.
16 VDD power_in Positive supply voltage for the digital control inputs, recommended 3.0 V to 9.0 V and the highest analog voltage reference.

Key specifications

Parameter Value
Manufacturer HANSCHIP semiconductor
Package SOP-16
Category Interface
Pins 16

CAD (KiCad official)

  • Symbol: 74HC4053DRG
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc4053drg-etched.step / 74hc4053drg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc4053drg.step / 74hc4053drg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HANSCHIP semiconductor datasheet (13 pp, sha256 fb1ec41f2801b9bf, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF