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74HC4052PWRG

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HANSCHIP semiconductor Analog Switches, Multiplexers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC4052PWRG

HANSCHIP semiconductor · Analog Switches, Multiplexers · TSSOP-16

74HC4052PWRG from HANSCHIP semiconductor, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Y0B bidirectional Independent input/output of switch B, channel 0, connected to ZB when A1=L, A0=L and enable is low.
2 Y2B bidirectional Independent input/output of switch B, channel 2, connected to ZB when A1=H, A0=L and enable is low.
3 ZB bidirectional Common input/output of switch B.
4 Y3B bidirectional Independent input/output of switch B, channel 3, connected to ZB when A1=H, A0=H and enable is low.
5 Y1B bidirectional Independent input/output of switch B, channel 1, connected to ZB when A1=L, A0=H and enable is low.
6 E input Active-low enable input; when high all switches are off (high impedance) regardless of A0 and A1.
7 VEE power_in Negative supply voltage; analog signals may swing down to VEE, with VEE between -6.0 V and 0 V and VDD-VEE not exceeding 9 V.
8 VSS power_in Ground; supply reference for the digital control inputs (A0, A1, enable), normally tied to VEE for digital multiplexing.
9 A1 input Channel select input 1 (MSB) shared by both switches.
10 A0 input Channel select input 0 (LSB) shared by both switches.
11 Y3A bidirectional Independent input/output of switch A, channel 3, connected to ZA when A1=H, A0=H and enable is low.
12 Y0A bidirectional Independent input/output of switch A, channel 0, connected to ZA when A1=L, A0=L and enable is low.
13 ZA bidirectional Common input/output of switch A.
14 Y1A bidirectional Independent input/output of switch A, channel 1, connected to ZA when A1=L, A0=H and enable is low.
15 Y2A bidirectional Independent input/output of switch A, channel 2, connected to ZA when A1=H, A0=L and enable is low.
16 VDD power_in Positive supply voltage, recommended 3.0 V to 9.0 V (absolute maximum 12 V).

Key specifications

Parameter Value
Manufacturer HANSCHIP semiconductor
Package TSSOP-16
Category Interface
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VDD -0.5 12 V 5
Supply voltage range (VDD-VEE) VDD-VEE -0.5 12 V 5
Static current IQ 2 μA VDD-VEE=12V 5
Input voltage range (lower limit) VI -0.5 V 5
High-level input current /IIH/ 1 μA VDD=5V, VI=VDD 5
Low-level input current /IIL/ 1 μA VDD=5V, VI=0V 5
Input clamp current IIK -20 20 mA VI<-0.5V 或 VI>VDD+0.5V 5
Input-output clamp current IIOK -20 20 mA VIO<VEE-0.5V 或 VIO>VDD+0.5V 5
Switch on current IT -25 25 mA VO=-0.5V～VDD+0.5V 5
VDD or GND current IDD, IGND -50 50 mA 5
Power dissipation PD 500 mW 5
Storage temperature TSTG -65 150 ℃ 5
Operating temperature (absolute maximum table) TOP -40 85 ℃ 5
Supply voltage VDD 3 5 9 V 5
Supply voltage VEE -6 0 V 5
Supply voltage difference VDD-VEE 3 9 V 5
Input voltage VI 0 V 5
Input rise/fall time tr,tf 1000 ns VCC=3.0V 5
Input rise/fall time tr,tf 500 ns VCC=5.0V 5
Input rise/fall time tr,tf 400 ns VCC=6.0V 5
Operating temperature (recommended) TOP -40 85 ℃ 5
On-state resistance (VDD-VEE=5V) RON 350 2500 Ω VDD-VEE=5V; Vis=0～VDD－VEE; 见图1 6
On-state resistance (VDD-VEE=9V) RON 80 245 Ω VDD-VEE=9V; Vis=0～VDD－VEE; 见图1 6
On-state resistance (VDD-VEE=5V) RON 115 340 Ω VDD-VEE=5V; Vis=0; 见图1 6
On-state resistance (VDD-VEE=9V) RON 50 160 Ω VDD-VEE=9V; Vis=0; 见图1 6
On-state resistance (VDD-VEE=5V) RON 120 365 Ω VDD-VEE=5V; Vis=VDD－VEE; 见图1 6
On-state resistance (VDD-VEE=9V) RON 65 200 Ω VDD-VEE=9V; Vis=VDD－VEE; 见图1 6
Off-state leakage current (all channels off) IOZZ 1000 nA 所有通道关断; 处于VDD 6
Off-state leakage current (any channel) IOZY 200 nA 任一通道关断; 处于VEE 6
Propagation delay Vis→Vos high-to-low (VDD=5V) tPHL 10 20 ns 注释1: RL=10KΩ到VEE; CL=50pF到VEE; 使能=VSS; Vis=VDD(方波) 7
Propagation delay Vis→Vos high-to-low (VDD=9V) tPHL 5 10 ns 注释1: RL=10KΩ到VEE; CL=50pF到VEE; 使能=VSS; Vis=VDD(方波) 7
Propagation delay Vis→Vos low-to-high (VDD=5V) tPLH 10 20 ns 注释1: RL=10KΩ到VEE; CL=50pF到VEE; 使能=VSS; Vis=VDD(方波) 7
Propagation delay Vis→Vos low-to-high (VDD=9V) tPLH 5 10 ns 注释1: RL=10KΩ到VEE; CL=50pF到VEE; 使能=VSS; Vis=VDD(方波) 7
Propagation delay An→Vos high-to-low (VDD=5V) tPHL 150 305 ns 注释2: RL=10KΩ; CL=50pF到VEE; 使能=VSS; An=VDD(方波) 7
Propagation delay An→Vos high-to-low (VDD=9V) tPHL 65 135 ns 注释2: RL=10KΩ; CL=50pF到VEE; 使能=VSS; An=VDD(方波) 7
Propagation delay An→Vos low-to-high (VDD=5V) tPLH 150 300 ns 注释2: RL=10KΩ; CL=50pF到VEE; 使能=VSS; An=VDD(方波) 7
Propagation delay An→Vos low-to-high (VDD=9V) tPLH 75 150 ns 注释2: RL=10KΩ; CL=50pF到VEE; 使能=VSS; An=VDD(方波) 7
Output disable time, high (VDD=5V) tPHZ 95 190 ns 注释3: RL=10KΩ; CL=50pF到VEE; 使能=VDD(方波) 7
Output disable time, high (VDD=9V) tPHZ 90 180 ns 注释3: RL=10KΩ; CL=50pF到VEE; 使能=VDD(方波) 7
Output disable time, low (VDD=5V) tPLZ 100 205 ns 注释3: RL=10KΩ; CL=50pF到VEE; 使能=VDD(方波) 7
Output disable time, low (VDD=9V) tPLZ 90 180 ns 注释3: RL=10KΩ; CL=50pF到VEE; 使能=VDD(方波) 7
Output enable time, high (VDD=5V) tPZH 130 260 ns 注释3: RL=10KΩ; CL=50pF到VEE; 使能=VDD(方波) 7
Output enable time, high (VDD=9V) tPZH 55 115 ns 注释3: RL=10KΩ; CL=50pF到VEE; 使能=VDD(方波) 7
Output enable time, low (VDD=5V) tPZL 120 240 ns 注释3: RL=10KΩ; CL=50pF到VEE; 使能=VDD(方波) 7
Output enable time, low (VDD=9V) tPZL 50 100 ns 注释3: RL=10KΩ; CL=50pF到VEE; 使能=VDD(方波) 7
Crosstalk, enable or select to output 50 mV 注释6: RL=10KΩ到VEE; CL=15pF到VEE; 使能或An=VDD(方波); 干扰为/Vos/峰值 7

CAD (KiCad official)

  • Symbol: 74HC4052PWRG
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc4052pwrg-etched.step / 74hc4052pwrg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc4052pwrg.step / 74hc4052pwrg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HANSCHIP semiconductor datasheet (12 pp, sha256 5eee2d121e3bea3c, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF