← Commit history

Initial commit: component/74hc4052pw

Ray ·f8ed992872 ·1mo ago
2 files changed +94
README.mdadded+60
@@ -0,0 +1,60 @@+# 74HC4052PW++**Nexperia** · Analog Switches, Multiplexers · TSSOP-16++74HC4052PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 2Y0 | bidirectional | Independent input or output of switch 2, channel 0. Analog signal path selected when E=L, S1=L, S0=L (routes 2Y0 <-> 2Z). |+| 2 | 2Y2 | bidirectional | Independent input or output of switch 2, channel 2. Analog signal path selected when E=L, S1=H, S0=L (routes 2Y2 <-> 2Z). |+| 3 | 2Z | bidirectional | Common input or output of switch 2 (analog SP4T pole). Routed to one of 2Y0..2Y3 according to S1/S0 when E is LOW. |+| 4 | 2Y3 | bidirectional | Independent input or output of switch 2, channel 3. Analog signal path selected when E=L, S1=H, S0=H (routes 2Y3 <-> 2Z). |+| 5 | 2Y1 | bidirectional | Independent input or output of switch 2, channel 1. Analog signal path selected when E=L, S1=L, S0=H (routes 2Y1 <-> 2Z). |+| 6 | E | input | Active-LOW enable input. When E is HIGH, all switches are turned off (high impedance on nY and nZ). When E is LOW, S1/S0 select which nYn connects to nZ. |+| 7 | VEE | power_in | Negative analog supply voltage. Sets the lower analog signal rail; VCC-VEE ranges from 2.0 V to 10.0 V. Typically GND for single-supply digital use or -5 V for +/-5 V analog signals. |+| 8 | GND | power_in | Digital ground reference (0 V). Reference for the digital control inputs (E, S0, S1). |+| 9 | S1 | input | Digital channel select input, MSB. Together with S0 selects which of nY0..nY3 is connected to nZ when E is LOW. |+| 10 | S0 | input | Digital channel select input, LSB. Together with S1 selects which of nY0..nY3 is connected to nZ when E is LOW. |+| 11 | 1Y3 | bidirectional | Independent input or output of switch 1, channel 3. Analog signal path selected when E=L, S1=H, S0=H (routes 1Y3 <-> 1Z). |+| 12 | 1Y0 | bidirectional | Independent input or output of switch 1, channel 0. Analog signal path selected when E=L, S1=L, S0=L (routes 1Y0 <-> 1Z). |+| 13 | 1Z | bidirectional | Common input or output of switch 1 (analog SP4T pole). Routed to one of 1Y0..1Y3 according to S1/S0 when E is LOW. |+| 14 | 1Y1 | bidirectional | Independent input or output of switch 1, channel 1. Analog signal path selected when E=L, S1=L, S0=H (routes 1Y1 <-> 1Z). |+| 15 | 1Y2 | bidirectional | Independent input or output of switch 1, channel 2. Analog signal path selected when E=L, S1=H, S0=L (routes 1Y2 <-> 1Z). |+| 16 | VCC | power_in | Positive supply voltage. Sets the upper analog signal rail and powers digital control logic. VCC-GND: 2.0 V to 10.0 V (74HC4052) or 4.5 V to 5.5 V (74HCT4052). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nexperia |+| Package | TSSOP-16 |+| Category | Interface |+| Pins | 16 |++## Ordering variants++Same part, different packaging or reel option.++- `74HC4052PW`+- `74HC4052PWD`+- `74HC4052PWBQ`+- `74HC4052PWBZ`++## CAD (KiCad official)++- Symbol: `74HC4052PW`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8579711898906124288) (25 pp, sha256 `1690fa0bf0610fdc`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74hc4052pw-datasheet.pdf)
page.jsonadded+34
@@ -0,0 +1,34 @@+{+  "slug": "74hc4052pw",+  "version": "0.1.0",+  "type": "component",+  "description": "Nexperia Analog Switches, Multiplexers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "interface",+    "74hc4052pw"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "74hc4052pw.kicad_sym",+    "74hc4052pw.kicad_mod",+    "74hc4052pw.glb",+    "74hc4052pw.step",+    "74hc4052pw.lbr",+    "docs/hero.png",+    "docs/74hc4052pw-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file