# 74HC4051PWRG

**HANSCHIP semiconductor** · Analog Switches, Multiplexers · TSSOP-16

74HC4051PWRG from HANSCHIP semiconductor, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y4 | passive | Independent analog input/output channel 4, switched to the common Z pin when A0-A2 select it and E is low. |
| 2 | Y6 | passive | Independent analog input/output channel 6, switched to the common Z pin when A0-A2 select it and E is low. |
| 3 | Z | passive | Common analog input/output pin shared by all eight switches; Y and Z voltages must stay between VEE and VDD. |
| 4 | Y7 | passive | Independent analog input/output channel 7, switched to the common Z pin when A0-A2 select it and E is low. |
| 5 | Y5 | passive | Independent analog input/output channel 5, switched to the common Z pin when A0-A2 select it and E is low. |
| 6 | E | input | Active-low enable input; when high, all switches are turned off (high-impedance) and A0-A2 are ignored. |
| 7 | VEE | power_in | Negative supply voltage; the datasheet lists VEE in the range -6.0 V to 0 V, and VDD−VEE must not exceed 9 V. |
| 8 | VSS | power_in | Ground reference for the digital control inputs; for digital-only multiplexing it is tied to VEE, typically to ground. |
| 9 | A2 | input | Channel select address input (most significant bit), with inputs referenced between VSS and VDD. |
| 10 | A1 | input | Channel select address input (middle bit), with inputs referenced between VSS and VDD. |
| 11 | A0 | input | Channel select address input (least significant bit), with inputs referenced between VSS and VDD. |
| 12 | Y3 | passive | Independent analog input/output channel 3, switched to the common Z pin when A0-A2 select it and E is low. |
| 13 | Y0 | passive | Independent analog input/output channel 0, switched to the common Z pin when A0-A2 select it and E is low. |
| 14 | Y1 | passive | Independent analog input/output channel 1, switched to the common Z pin when A0-A2 select it and E is low. |
| 15 | Y2 | passive | Independent analog input/output channel 2, switched to the common Z pin when A0-A2 select it and E is low. |
| 16 | VDD | power_in | Positive supply voltage; the datasheet gives VDD in the range 3.0 V to 9.0 V (absolute maximum -0.5 V to +12 V) referenced to VSS. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | HANSCHIP semiconductor |
| Package | TSSOP-16 |
| Category | Interface |
| Pins | 16 |

## CAD (KiCad official)

- Symbol: `74HC4051PWRG`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `74hc4051pwrg-etched.step` / `74hc4051pwrg-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc4051pwrg.step` / `74hc4051pwrg.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [HANSCHIP semiconductor datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586209292558589952) (15 pp, sha256 `7296e952966e174f`, retrieved 2026-10-09, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/74hc4051pwrg-datasheet.pdf)