component

74HC4051PW

Public Made by Adom

by adom

Nexperia Analog Switches, Multiplexers, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentinterface74hc4051pw
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs 74hc4051pw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 2mo ago
74hc4051pw-etched.fit.json 74hc4051pw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74hc4051pw-etched.glb 74hc4051pw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74hc4051pw-etched.step 74hc4051pw: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
74hc4051pw.glb Publish 0.1.0 · Ray 2mo ago
74hc4051pw.kicad_mod Publish 0.1.0 · Ray 2mo ago
74hc4051pw.kicad_sym Publish 0.1.0 · Ray 2mo ago
74hc4051pw.lbr rebuild the library on adom-lbr 2.32.0. The published copy was built by 2.18.0, which imported every KiCad roundrect an… · Ray 2mo ago
74hc4051pw.step Publish 0.1.0 · Ray 2mo ago
package.json Publish 0.2.0 · Ray 2mo ago
pads.json pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left) · Ray 2mo ago
page.json 74hc4051pw: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md 74hc4051pw: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray 1mo ago

74HC4051PW

Nexperia · Analog Switches, Multiplexers · TSSOP-16

74HC4051PW from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Y4 bidirectional Independent analog input/output channel 4. Connected to common Z when S2=H, S1=L, S0=L and E=L. Analog signal range VEE to VCC.
2 Y6 bidirectional Independent analog input/output channel 6. Connected to common Z when S2=H, S1=H, S0=L and E=L. Analog signal range VEE to VCC.
3 Z bidirectional Common analog input/output (SP8T pole). Connected to the selected Y0-Y7 channel per the S2/S1/S0 select code when enable E is LOW.
4 Y7 bidirectional Independent analog input/output channel 7. Connected to common Z when S2=H, S1=H, S0=H and E=L. Analog signal range VEE to VCC.
5 Y5 bidirectional Independent analog input/output channel 5. Connected to common Z when S2=H, S1=L, S0=H and E=L. Analog signal range VEE to VCC.
6 ~E input Enable input, active LOW. When LOW, the selected switch (per S0/S1/S2) is ON; when HIGH, all switches are OFF (Z is isolated from all Y channels).
7 VEE power_in Negative analog supply voltage rail. Sets the lower analog signal range; may be tied to GND for single-supply operation or to a negative rail (VCC-VEE up to 10 V for HC, 5.5 V-referenced for HCT).
8 GND power_in Ground supply voltage (0 V reference). Logic reference for the digital select and enable inputs.
9 S2 input Digital channel-select input bit 2 (MSB of the 3-bit S2:S0 selector). CMOS logic level referenced to VCC/GND.
10 S1 input Digital channel-select input bit 1. CMOS logic level referenced to VCC/GND.
11 S0 input Digital channel-select input bit 0 (LSB of the 3-bit S2:S0 selector). CMOS logic level referenced to VCC/GND.
12 Y3 bidirectional Independent analog input/output channel 3. Connected to common Z when S2=L, S1=H, S0=H and E=L. Analog signal range VEE to VCC.
13 Y0 bidirectional Independent analog input/output channel 0. Connected to common Z when S2=L, S1=L, S0=L and E=L. Analog signal range VEE to VCC.
14 Y1 bidirectional Independent analog input/output channel 1. Connected to common Z when S2=L, S1=L, S0=H and E=L. Analog signal range VEE to VCC.
15 Y2 bidirectional Independent analog input/output channel 2. Connected to common Z when S2=L, S1=H, S0=L and E=L. Analog signal range VEE to VCC.
16 VCC power_in Positive supply voltage. 2.0-10.0 V for 74HC4051; 4.5-5.5 V for 74HCT4051. Also sets the upper analog signal range with VEE.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-16
Category Interface
Pins 16

Ordering variants

  • 74HC4051PW
  • 74HC4051PWD
  • 74HC4051PWBQ
  • 74HC4051PWBZ

CAD (KiCad official)

  • Symbol: 74HC4051PW
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc4051pw-etched.step / 74hc4051pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc4051pw.step / 74hc4051pw.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
74hc4051pw.step 205 KB You want the bare part, or you mark your own boards.
74hc4051pw-etched.step 2.2 MB You want the part with 74HC4051PW already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 562 faces against 255 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (28 pp, sha256 e5b40e804e4dea04, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF