component
74HC4051N
Public Made by Adomby adom
HGSEMI Analog Switches, Multiplexers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC4051N
HGSEMI · Analog Switches, Multiplexers · DIP-16
74HC4051N from HGSEMI, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y4 | bidirectional | Independent analog input/output channel 4, which connects to common Z when selected by A0-A2 with E low; analog voltage must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 2 | Y6 | bidirectional | Independent analog input/output channel 6, which connects to common Z when selected by A0-A2 with E low; analog voltage must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 3 | Z | bidirectional | Common analog input/output that connects to whichever Y channel is selected; Y and Z voltages must not exceed VDD or fall below VEE, and switch current is limited to ±10 mA. |
| 4 | Y7 | bidirectional | Independent analog input/output channel 7, which connects to common Z when selected by A0-A2 with E low; analog voltage must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 5 | Y5 | bidirectional | Independent analog input/output channel 5, which connects to common Z when selected by A0-A2 with E low; analog voltage must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 6 | E | input | Active-low enable input; when driven high, all switches are turned off (high impedance) and A0-A2 are ignored, while the datasheet's absolute maximum input voltage is VDD+0.5 V relative to VSS. |
| 7 | VEE | power_in | Negative power supply; the datasheet limits VDD−VEE to 9 V maximum and VEE to −12 V to +0.5 V (referenced to the supply) in absolute maximum ratings. |
| 8 | VSS | power_in | Ground reference for the digital control inputs (A0-A2 and E); when the device is used as a digital multiplexer, VEE and VSS are tied together, typically to ground. |
| 9 | A2 | input | Channel select input bit 2 (most significant) that, with A1 and A0, selects one of Y0-Y7 when E is low; the datasheet notes these inputs must not be changed to switch channels while E is high because they are ignored. |
| 10 | A1 | input | Channel select input bit 1 that, with A2 and A0, selects one of Y0-Y7 when E is low; digital input range is 0 V to VDD. |
| 11 | A0 | input | Channel select input bit 0 (least significant) that, with A2 and A1, selects one of Y0-Y7 when E is low; digital input range is 0 V to VDD. |
| 12 | Y3 | bidirectional | Independent analog input/output channel 3, which connects to common Z when selected by A0-A2 with E low; analog voltage must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 13 | Y0 | bidirectional | Independent analog input/output channel 0, which connects to common Z when selected by A0-A2 with E low; analog voltage must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 14 | Y1 | bidirectional | Independent analog input/output channel 1, which connects to common Z when selected by A0-A2 with E low; analog voltage must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 15 | Y2 | bidirectional | Independent analog input/output channel 2, which connects to common Z when selected by A0-A2 with E low; analog voltage must stay between VEE and VDD and switch current is limited to ±10 mA. |
| 16 | VDD | power_in | Positive power supply; the datasheet specifies VDD−VEE of 3.0 V to 9.0 V, with absolute maximum VDD of −0.5 V to +12 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | DIP-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive supply voltage VDD | VDD | -0.5 | 12 | V | Tamb=25℃ unless otherwise specified | 5 | |
| Negative supply voltage VEE | VEE | -12 | 0.5 | V | Referenced to power supply, as printed | 5 | |
| Input voltage range | VI | -0.5 | V | Upper limit printed as VDD+0.5 V (not numeric) | 5 | ||
| Switch on-state current | I | -10 | 10 | mA | 5 | ||
| Power dissipation (DIP16) | PD | 700 | mW | DIP16, Tamb -40℃~+85℃ | 5 | ||
| Power dissipation per output | Po | 100 | mW | 5 | |||
| Operating ambient temperature | Tamb | -40 | 85 | ℃ | 5 | ||
| Storage temperature | Tstg | -65 | 150 | ℃ | 5 | ||
| Soldering temperature (DIP) | TL | 245 | ℃ | 10 s, DIP package | 5 | ||
| Supply voltage VDD (recommended) | VDD | 3 | 5 | 9 | V | Tamb=25℃; RL=10kΩ; CL=50pF; Vis=VDD=5V (square wave) | 5 |
| Supply voltage VEE (recommended) | VEE | -6 | 0 | V | Tamb=25℃; RL=10kΩ; CL=50pF; Vis=VDD=5V (square wave) | 5 | |
| Supply voltage VDD-VEE (recommended) | VDD-VEE | 3 | 9 | V | Tamb=25℃; RL=10kΩ; CL=50pF; Vis=VDD=5V (square wave) | 5 | |
| Input voltage (recommended) | VI | 0 | V | Upper limit printed as VDD (not numeric) | 5 | ||
| Output disable time (high to off) | tPHZ | 85 | 170 | ns | E→Z or E→Yn | 5 | |
| Output disable time (low to off) | tPLZ | 115 | 230 | ns | E→Z or E→Yn | 5 | |
| Output enable time (off to high/low) | tPZH, tPZL | 40 | 80 | ns | E→Z or E→Yn | 5 | |
| Propagation delay Z→Yn / Yn→Z | tPHL, tPLH | 15 | 30 | ns | VDD=5V; E=VSS; Vis=VDD (square wave); Tamb=25℃ | 7 | |
| Propagation delay Z→Yn / Yn→Z | tPHL, tPLH | 5 | 10 | ns | VDD=9V; E=VSS; Vis=VDD (square wave); Tamb=25℃ | 7 | |
| Propagation delay An→Yn / An→Z (high to low) | tPHL | 150 | 300 | ns | VDD=5V; E=VSS; An=VDD (square wave) | 7 | |
| Propagation delay An→Yn / An→Z (high to low) | tPHL | 60 | 120 | ns | VDD=9V; E=VSS; An=VDD (square wave) | 7 | |
| Propagation delay An→Yn / An→Z (low to high) | tPLH | 150 | 300 | ns | VDD=5V; E=VSS; An=VDD (square wave); Vis=VDD | 7 | |
| Propagation delay An→Yn / An→Z (low to high) | tPLH | 65 | 130 | ns | VDD=9V; E=VSS; An=VDD (square wave); Vis=VDD | 7 | |
| Output disable time E→Yn/Z (high to off) | tPHZ | 120 | 240 | ns | VDD=5V; E=VDD (square wave); Vis=VDD | 7 | |
| Output disable time E→Yn/Z (high to off) | tPHZ | 90 | 180 | ns | VDD=9V; E=VDD (square wave); Vis=VDD | 7 | |
| Output disable time E→Yn/Z (low to off) | tPLZ | 145 | 290 | ns | VDD=5V; E=VDD (square wave); Vis=VEE | 7 | |
| Output disable time E→Yn/Z (low to off) | tPLZ | 120 | 240 | ns | VDD=9V; E=VDD (square wave); Vis=VEE | 7 | |
| Output enable time E→Yn/Z (off to high) | tPZH | 140 | 280 | ns | VDD=5V; E=VDD (square wave); Vis=VDD | 7 | |
| Output enable time E→Yn/Z (off to high) | tPZH | 55 | 110 | ns | VDD=9V; E=VDD (square wave); Vis=VDD | 7 | |
| Output enable time E→Yn/Z (off to low) | tPZL | 140 | 280 | ns | VDD=5V; E=VDD (square wave); Vis=VEE | 7 | |
| Output enable time E→Yn/Z (off to low) | tPZL | 55 | 110 | ns | VDD=9V; E=VDD (square wave); Vis=VEE | 8 | |
| Quiescent supply current | IDD | 20 | µA | Tamb=25℃; VI=VDD or VSS, IO=0A; VDD=5V | 6 | ||
| Quiescent supply current | IDD | 40 | µA | Tamb=25℃; VI=VDD or VSS, IO=0A; VDD=9V | 6 | ||
| High-level input voltage | VIH | 3.5 | V | Tamb=25℃; /IO/<1µA; VDD=5V, VO=0.5V or 4.5V | 6 | ||
| High-level input voltage | VIH | 7 | V | Tamb=25℃; /IO/<1µA; VDD=9V, VO=0.5V or 8V | 6 | ||
| Low-level input voltage | VIL | 1.5 | V | Tamb=25℃; /IO/<1µA; VDD=5V, VO=0.5V or 4.5V | 6 | ||
| Low-level input voltage | VIL | 3 | V | Tamb=25℃; /IO/<1µA; VDD=9V, VO=0.5V or 8V | 6 | ||
| Input leakage current | ILI | 0.3 | µA | Tamb=25℃; VI=0V or 9V, VDD=9V | 6 | ||
| 3-state output leakage current (to VDD) | IOZ | 1.6 | µA | Tamb=25℃; VDD=9V; output to VDD | 6 | ||
| 3-state output leakage current (to VSS) | IOZ | -1.6 | µA | Tamb=25℃; VDD=9V; output to VSS | 6 | ||
| Off-state leakage current (all channels off) | IL(OFF) | 1000 | nA | Tamb=25℃; VSS=VEE; VDD-VEE=9V; all channels off; E=VDD | 6 | ||
| Off-state leakage current (any channel off) | IL(OFF) | 200 | nA | Tamb=25℃; VSS=VEE; VDD-VEE=9V; any channel off; E=VSS | 6 | ||
| On-resistance | RON | 350 | 2500 | Ω | Tamb=25℃; Vis=0V~VDD-VEE; VDD-VEE=5V | 6 | |
| On-resistance | RON | 80 | 245 | Ω | Tamb=25℃; Vis=0V~VDD-VEE; VDD-VEE=9V | 6 | |
| On-resistance | RON | 115 | 340 | Ω | Tamb=25℃; Vis=0V; VDD-VEE=5V | 6 | |
| On-resistance | RON | 50 | 160 | Ω | Tamb=25℃; Vis=0V; VDD-VEE=9V | 6 | |
| On-resistance | RON | 120 | 365 | Ω | Tamb=25℃; Vis=VDD-VEE; VDD-VEE=5V | 6 | |
| On-resistance | RON | 65 | 200 | Ω | Tamb=25℃; Vis=VDD-VEE; VDD-VEE=9V | 6 | |
| On-resistance change between any two channels | ΔRON | 25 | Ω | Tamb=25℃; Vis=0V~VDD-VEE; VDD-VEE=5V | 6 | ||
| On-resistance change between any two channels | ΔRON | 10 | Ω | Tamb=25℃; Vis=0V~VDD-VEE; VDD-VEE=9V | 6 | ||
| Quiescent supply current | IDD | 150 | µA | Tamb=85℃; VI=VDD or VSS, IO=0A; VDD=5V | 7 | ||
| Quiescent supply current | IDD | 300 | µA | Tamb=85℃; VI=VDD or VSS, IO=0A; VDD=9V | 7 | ||
| High-level input voltage | VIH | 3.5 | V | Tamb=85℃; /IO/<1µA; VDD=5V, VO=0.5V or 4.5V | 7 | ||
| High-level input voltage | VIH | 7 | V | Tamb=85℃; /IO/<1µA; VDD=9V, VO=0.5V or 8V | 7 | ||
| Low-level input voltage | VIL | 1.5 | V | Tamb=85℃; /IO/<1µA; VDD=5V, VO=0.5V or 4.5V | 7 | ||
| Low-level input voltage | VIL | 3 | V | Tamb=85℃; /IO/<1µA; VDD=9V, VO=0.5V or 8V | 7 | ||
| Input leakage current | ILI | 1 | µA | Tamb=85℃; VI=0V or 9V, VDD=9V | 7 | ||
| 3-state output leakage current (to VDD) | IOZ | 12 | µA | Tamb=85℃; VDD=9V; output to VDD | 7 | ||
| 3-state output leakage current (to VSS) | IOZ | -12 | µA | Tamb=85℃; VDD=9V; output to VSS | 7 | ||
| Digital input capacitance | Ci | 7.5 | pF | 6 | |||
| Crosstalk between channels | Vct | 50 | mV | RL=10kΩ; CL=15pF; E or An=VDD (square wave); VDD=9V | 8 |
CAD (KiCad official)
- Symbol:
74HC4051N - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
74hc4051n-etched.step/74hc4051n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc4051n.step/74hc4051n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (16 pp, sha256
e76afd9e53c61c06, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).