component
74HC4051-MS
Public Made by Adomby adom
MSKSEMI Analog Switches, Multiplexers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC4051-MS
MSKSEMI · Analog Switches, Multiplexers · SOP-16
74HC4051-MS from MSKSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 4 | passive | Analog switch channel 4; the signal path is enabled when the binary address selects channel 4 and INH is low, with analog voltage limited to 0 to VDD-VEE. |
| 2 | 6 | passive | Analog switch channel 6; the signal path is enabled when the binary address selects channel 6 and INH is low, with analog voltage limited to 0 to VDD-VEE. |
| 3 | COM | passive | Common analog OUT/IN terminal that connects to the one channel selected by A, B, C when INH is low; analog voltage limited to 0 to VDD-VEE. |
| 4 | 7 | passive | Analog switch channel 7; the signal path is enabled when the binary address selects channel 7 and INH is low, with analog voltage limited to 0 to VDD-VEE. |
| 5 | 5 | passive | Analog switch channel 5; the signal path is enabled when the binary address selects channel 5 and INH is low, with analog voltage limited to 0 to VDD-VEE. |
| 6 | INH | input | Enable control input; when INH is high (VDD) all channels are off, per the truth table. |
| 7 | VEE | power_in | Negative supply for the analog switches; recommended VDD-VEE range is 0 to 15 V. |
| 8 | VSS | power_in | Digital ground; recommended DC supply voltage VDD-VSS is 3 to 15 V and absolute maximum is -0.5 to 18 V. |
| 9 | C | input | Channel select control input (most significant address bit); control input voltage range is 0 to VDD-VSS. |
| 10 | B | input | Channel select control input (middle address bit); control input voltage range is 0 to VDD-VSS. |
| 11 | A | input | Channel select control input (least significant address bit); control input voltage range is 0 to VDD-VSS. |
| 12 | 3 | passive | Analog switch channel 3; the signal path is enabled when the binary address selects channel 3 and INH is low, with analog voltage limited to 0 to VDD-VEE. |
| 13 | 0 | passive | Analog switch channel 0; the signal path is enabled when the binary address selects channel 0 and INH is low, with analog voltage limited to 0 to VDD-VEE. |
| 14 | 1 | passive | Analog switch channel 1; the signal path is enabled when the binary address selects channel 1 and INH is low, with analog voltage limited to 0 to VDD-VEE. |
| 15 | 2 | passive | Analog switch channel 2; the signal path is enabled when the binary address selects channel 2 and INH is low, with analog voltage limited to 0 to VDD-VEE. |
| 16 | VDD | power_in | Positive supply; recommended DC supply voltage VDD-VSS is 3 to 15 V and absolute maximum is 18 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | MSKSEMI |
| Package | SOP-16 |
| Category | Interface |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage VDD-VSS (absolute maximum) | VDD-VSS | -0.5 | 18 | V | 3 | ||
| Analog supply voltage VDD-VEE (absolute maximum) | VDD-VEE | 18 | V | 3 | |||
| Power dissipation (absolute maximum) | PD | 500 | mW | 3 | |||
| Operating temperature (absolute maximum) | TA | -40 | 85 | ℃ | 3 | ||
| Storage temperature (absolute maximum) | TS | -65 | 150 | ℃ | 3 | ||
| Lead soldering temperature (absolute maximum) | TW | 260 | ℃ | 10s | 3 | ||
| DC supply voltage VDD-VSS (recommended) | VDD-VSS | 3 | 15 | V | 4 | ||
| Analog supply voltage VDD-VEE (recommended) | VDD-VEE | 0 | 15 | V | 4 | ||
| Control input voltage (recommended) | VIS | 0 | V | printed max is VDD-VSS | 4 | ||
| Analog input/output voltage (recommended) | VIN, VOUT | 0 | V | printed max is VDD-VEE | 4 | ||
| Operating temperature (recommended) | TA | -40 | 85 | ℃ | 4 | ||
| High-level input voltage VIH, VDD=5V | VIH | 3.5 | V | VDD=5V; VIH=VDD through 1k; VEE=VSS, RL=1kΩ to VSS, IIS<2uA on all OFF Channels | 4 | ||
| High-level input voltage VIH, VDD=10V | VIH | 7 | V | VDD=10V; VIH=VDD through 1k; VEE=VSS, RL=1kΩ to VSS, IIS<2uA on all OFF Channels | 4 | ||
| High-level input voltage VIH, VDD=15V | VIH | 11 | V | VDD=15V; VIH=VDD through 1k; VEE=VSS, RL=1kΩ to VSS, IIS<2uA on all OFF Channels | 4 | ||
| Low-level input voltage VIL, VDD=5V | VIL | 1.5 | V | VDD=5V; VIL=VDD through 1k | 4 | ||
| Low-level input voltage VIL, VDD=10V | VIL | 3 | V | VDD=10V; VIL=VDD through 1k | 4 | ||
| Low-level input voltage VIL, VDD=15V | VIL | 4 | V | VDD=15V; VIL=VDD through 1k | 4 | ||
| Channel OFF leakage current IOFF | IOFF | -100 | 100 | nA | VDD=18V; 输入输出通道关闭,INH=VDD | 4 | |
| Input current IIN | IIN | -0.1 | 0.01 | 0.1 | uA | VDD=18V; VIN=VDD or VSS | 4 |
| Quiescent supply current IDD, VDD=5V | IDD | 0.01 | 5 | uA | VDD=5V; VIN=VDD or VSS | 4 | |
| Quiescent supply current IDD, VDD=10V | IDD | 0.01 | 10 | uA | VDD=10V; VIN=VDD or VSS | 4 | |
| Quiescent supply current IDD, VDD=15V | IDD | 0.01 | 20 | uA | VDD=15V; VIN=VDD or VSS | 4 | |
| On-resistance RON, VDD=5V (value printed as single number, typ assumed) | RON | 150 | Ω | VDD=5V; 0≤VIS≤VDD | 4 | ||
| On-resistance RON, VDD=10V (value printed as single number, typ assumed) | RON | 80 | Ω | VDD=10V; 0≤VIS≤VDD | 4 | ||
| On-resistance RON, VDD=15V (value printed as single number, typ assumed) | RON | 60 | Ω | VDD=15V; 0≤VIS≤VDD | 4 | ||
| Adjacent channel on-resistance difference △RON, VDD=5V (typ assumed) | △RON | 15 | Ω | VDD=5V; 0≤VIS≤VDD | 4 | ||
| Adjacent channel on-resistance difference △RON, VDD=10V (typ assumed) | △RON | 10 | Ω | VDD=10V; 0≤VIS≤VDD | 4 | ||
| Adjacent channel on-resistance difference △RON, VDD=15V (typ assumed) | △RON | 5 | Ω | VDD=15V; 0≤VIS≤VDD | 4 | ||
| Input capacitance CIN (typ assumed) | CIN | 7.5 | pF | VDD=5V; 任意输入端 | 4 | ||
| Channel input capacitance CIS (typ assumed) | CIS | 5 | pF | VDD=5V | 4 | ||
| Output capacitance COS (typ assumed) | COS | 9 | pF | 4 | |||
| On-channel capacitance CIOS (typ assumed) | CIOS | 0.2 | pF | 4 | |||
| Propagation delay signal input to output, VDD=5V (typ assumed) | tpd | 15 | ns | VDD=5V; VIS=VDD, RL=200k, CL=50pF | 4 | ||
| Propagation delay signal input to output, VDD=10V (typ assumed) | tpd | 10 | ns | VDD=10V; VIS=VDD, RL=200k, CL=50pF | 4 | ||
| Propagation delay signal input to output, VDD=15V (typ assumed) | tpd | 7 | ns | VDD=15V; VIS=VDD, RL=200k, CL=50pF | 4 | ||
| Propagation delay address to signal OUT, VDD=5V (typ assumed) | tpd | 100 | ns | VDD=5V; CL=50pF, RL=10k | 4 | ||
| Propagation delay address to signal OUT, VDD=10V (typ assumed) | tpd | 80 | ns | VDD=10V; CL=50pF, RL=10k | 4 | ||
| Propagation delay address to signal OUT, VDD=15V (typ assumed) | tpd | 50 | ns | VDD=15V; CL=50pF, RL=10k | 4 | ||
| Propagation delay inhibit to signal OUT, channel turning ON, VDD=5V (typ assumed) | tpd | 100 | ns | VDD=5V; CL=50pF, RL=1k | 5 | ||
| Propagation delay inhibit to signal OUT, channel turning ON, VDD=10V (typ assumed) | tpd | 50 | ns | VDD=10V; CL=50pF, RL=1k | 5 | ||
| Propagation delay inhibit to signal OUT, channel turning ON, VDD=15V (typ assumed) | tpd | 30 | ns | VDD=15V; CL=50pF, RL=1k | 5 | ||
| Propagation delay inhibit to signal OUT, channel turning OFF, VDD=5V (typ assumed) | tpd | 100 | ns | VDD=5V; CL=50pF, RL=10k | 5 | ||
| Propagation delay inhibit to signal OUT, channel turning OFF, VDD=10V (typ assumed) | tpd | 50 | ns | VDD=10V; CL=50pF, RL=10k | 5 | ||
| Propagation delay inhibit to signal OUT, channel turning OFF, VDD=15V (typ assumed) | tpd | 30 | ns | VDD=15V; CL=50pF, RL=10k | 5 |
CAD (KiCad official)
- Symbol:
74HC4051-MS - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
74hc4051-ms-etched.step/74hc4051-ms-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc4051-ms.step/74hc4051-ms.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: MSKSEMI datasheet (7 pp, sha256
609e394ab50673ca, retrieved 2026-10-20, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).