component
74HC4046APW-Q100J
Public Made by Adomby adom
Nexperia Clock Generators / Frequency Synthesizers / PLL, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC4046APW-Q100J
Nexperia · Clock Generators / Frequency Synthesizers / PLL · TSSOP-16
74HC4046APW-Q100J from Nexperia, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PCP_OUT | output | Phase comparator pulse output. |
| 2 | PC1_OUT | output | Phase comparator 1 output (EXCLUSIVE-OR). |
| 3 | COMP_IN | input | Comparator input, common to all three phase comparators; can be driven directly from VCO_OUT or via a frequency divider. |
| 4 | VCO_OUT | output | VCO output, which can be connected directly to COMP_IN or via a frequency divider. |
| 5 | INH | input | Inhibit input; LOW enables the VCO and demodulator, HIGH turns both off to minimize standby power. |
| 6 | C1A | passive | Capacitor C1 connection A, with C1 connected between C1A and C1B. |
| 7 | C1B | passive | Capacitor C1 connection B, with C1 connected between C1A and C1B. |
| 8 | GND | power_in | Ground (0 V). |
| 9 | VCO_IN | input | VCO input with high input impedance, driven from the low-pass filter. |
| 10 | DEM_OUT | output | Demodulator output equal to the VCO input voltage; use a series resistor Rs to GND if used, leave open if unused. |
| 11 | R1 | passive | Resistor R1 connection, with R1 connected between this pin and GND to set VCO frequency range. |
| 12 | R2 | passive | Resistor R2 connection, with R2 connected to GND to give the VCO a frequency offset. |
| 13 | PC2_OUT | output | Phase comparator 2 output (edge-triggered J-K flip-flop). |
| 14 | SIG_IN | input | Signal input to the self-biasing amplifier; direct coupling for standard HC logic swings, capacitive coupling for smaller swings. |
| 15 | PC3_OUT | output | Phase comparator 3 output (edge-triggered RS flip-flop). |
| 16 | VCC | power_in | Supply voltage; VCO section 3.0 V to 6.0 V, digital section 2.0 V to 6.0 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | TSSOP-16 |
| Category | Clock and Timing |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 10 | ||
| Input clamping current | IIK | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V (printed ±20) | 10 | ||
| Output clamping current | IOK | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V (printed ±20) | 10 | ||
| Output current | IO | 25 | mA | -0.5 V < VO < VCC + 0.5 V (printed ±25) | 10 | ||
| Supply current | ICC | 50 | mA | 10 | |||
| Ground current | IGND | -50 | mA | 10 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 10 | ||
| Total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C; SOT403-1 derates 8.5 mW/K above 91 °C | 10 | ||
| Supply voltage | VCC | 3 | 5 | 6 | V | 10 | |
| Supply voltage when VCO is not used | VCC | 2 | 5 | 6 | V | when VCO is not used | 10 |
| Input voltage | VI | 0 | 6 | V | 0 to VCC | 10 | |
| Output voltage | VO | 0 | 6 | V | 0 to VCC | 10 | |
| Input transition rise and fall rate | Δt/ΔV | 625 | ns/V | pin INH; VCC = 2.0 V | 10 | ||
| Input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | pin INH; VCC = 4.5 V | 10 | |
| Input transition rise and fall rate | Δt/ΔV | 83 | ns/V | pin INH; VCC = 6.0 V | 10 | ||
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 10 | |
| HIGH-level input voltage SIG_IN, COMP_IN | VIH | 1.5 | 1.2 | V | DC coupled; VCC = 2.0 V; 25 °C | 11 | |
| HIGH-level input voltage SIG_IN, COMP_IN | VIH | 3.15 | 2.4 | V | DC coupled; VCC = 4.5 V; 25 °C | 11 | |
| HIGH-level input voltage SIG_IN, COMP_IN | VIH | 4.2 | 3.2 | V | DC coupled; VCC = 6.0 V; 25 °C | 11 | |
| LOW-level input voltage SIG_IN, COMP_IN | VIL | 0.8 | 0.5 | V | DC coupled; VCC = 2.0 V; 25 °C | 11 | |
| LOW-level input voltage SIG_IN, COMP_IN | VIL | 2.1 | 1.35 | V | DC coupled; VCC = 4.5 V; 25 °C | 11 | |
| LOW-level input voltage SIG_IN, COMP_IN | VIL | 2.8 | 1.8 | V | DC coupled; VCC = 6.0 V; 25 °C | 11 | |
| HIGH-level output voltage PCP_OUT, PCn_OUT | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; 25 °C | 11 | |
| HIGH-level output voltage PCP_OUT, PCn_OUT | VOH | 3.98 | 4.32 | V | VI = VIH or VIL; IO = -4 mA; VCC = 4.5 V; 25 °C | 11 | |
| HIGH-level output voltage PCP_OUT, PCn_OUT | VOH | 5.48 | 5.81 | V | VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; 25 °C | 11 | |
| HIGH-level output voltage PCP_OUT, PCn_OUT | VOH | 3.7 | V | VI = VIH or VIL; IO = -4 mA; VCC = 4.5 V; -40 °C to +125 °C | 11 | ||
| LOW-level output voltage PCP_OUT, PCn_OUT | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 4.5 V; 25 °C | 11 | |
| LOW-level output voltage PCP_OUT, PCn_OUT | VOL | 0.15 | 0.26 | V | VI = VIH or VIL; IO = 4 mA; VCC = 4.5 V; 25 °C | 11 | |
| LOW-level output voltage PCP_OUT, PCn_OUT | VOL | 0.16 | 0.26 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; 25 °C | 11 | |
| LOW-level output voltage PCP_OUT, PCn_OUT | VOL | 0.4 | V | VI = VIH or VIL; IO = 4 mA; VCC = 4.5 V; -40 °C to +125 °C | 11 | ||
| Input leakage current SIG_IN, COMP_IN | II | 30 | μA | VI = VCC or GND; VCC = 6.0 V; 25 °C (printed ±30) | 11 | ||
| Input leakage current SIG_IN, COMP_IN | II | 45 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C (printed ±45) | 11 | ||
| OFF-state output current PC2_OUT | IOZ | 0.5 | μA | VI = VIH or VIL; VO = VCC or GND; VCC = 6.0 V; 25 °C (printed ±0.5) | 11 | ||
| OFF-state output current PC2_OUT | IOZ | 10 | μA | VI = VIH or VIL; VO = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C (printed ±10) | 11 | ||
| HIGH-level input voltage INH | VIH | 3.15 | 2.4 | V | INH; VCC = 4.5 V; 25 °C | 12 | |
| LOW-level input voltage INH | VIL | 2.1 | 1.35 | V | INH; VCC = 4.5 V; 25 °C | 12 | |
| LOW-level output voltage C1A, C1B | VOL | 0.4 | V | C1A, C1B; VI = VIH or VIL; IO = 4 mA; VCC = 4.5 V; 25 °C | 12 | ||
| LOW-level output voltage C1A, C1B | VOL | 0.54 | V | C1A, C1B; VI = VIH or VIL; IO = 4 mA; VCC = 4.5 V; -40 °C to +125 °C | 12 | ||
| Input leakage current INH, VCO_IN | II | 0.1 | μA | VI = VCC or GND; VCC = 6.0 V; 25 °C (printed ±0.1) | 12 | ||
| Input leakage current INH, VCO_IN | II | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C (printed ±1) | 12 | ||
| Resistor 1 | R1 | 3 | 300 | kΩ | VCC = 3.0 V to 6.0 V; 25 °C | 12 | |
| Resistor 2 | R2 | 3 | 300 | kΩ | VCC = 3.0 V to 6.0 V; 25 °C | 12 | |
| Capacitor 1 | C1 | 40 | pF | VCC = 3.0 V to 6.0 V; max printed as no limit | 12 | ||
| Input voltage on pin VCO_IN | VVCO_IN | 1.1 | 1.9 | V | over the range specified for R1; VCC = 3.0 V | 12 | |
| Input voltage on pin VCO_IN | VVCO_IN | 1.1 | 3.4 | V | over the range specified for R1; VCC = 4.5 V | 12 | |
| Input voltage on pin VCO_IN | VVCO_IN | 1.1 | 4.9 | V | over the range specified for R1; VCC = 6.0 V | 12 | |
| Propagation delay SIG_IN, COMP_IN to PC1_OUT | tpd | 23 | 40 | ns | VCC = 4.5 V; 25 °C; CL = 50 pF | 15 | |
| Propagation delay SIG_IN, COMP_IN to PC1_OUT | tpd | 60 | ns | VCC = 4.5 V; -40 °C to +125 °C; CL = 50 pF | 15 | ||
| Propagation delay SIG_IN, COMP_IN to PCP_OUT | tpd | 35 | 68 | ns | VCC = 4.5 V; 25 °C; CL = 50 pF | 15 | |
| Propagation delay SIG_IN, COMP_IN to PCP_OUT | tpd | 102 | ns | VCC = 4.5 V; -40 °C to +125 °C; CL = 50 pF | 15 | ||
| Propagation delay SIG_IN, COMP_IN to PC3_OUT | tpd | 28 | 54 | ns | VCC = 4.5 V; 25 °C; CL = 50 pF | 15 | |
| Propagation delay SIG_IN, COMP_IN to PC3_OUT | tpd | 81 | ns | VCC = 4.5 V; -40 °C to +125 °C; CL = 50 pF | 15 | ||
| Enable time SIG_IN, COMP_IN to PC2_OUT | ten | 30 | 56 | ns | VCC = 4.5 V; 25 °C; CL = 50 pF | 15 | |
| Enable time SIG_IN, COMP_IN to PC2_OUT | ten | 84 | ns | VCC = 4.5 V; -40 °C to +125 °C; CL = 50 pF | 15 | ||
| Disable time SIG_IN, COMP_IN to PC2_OUT | tdis | 36 | 65 | ns | VCC = 4.5 V; 25 °C; CL = 50 pF | 15 | |
| Disable time SIG_IN, COMP_IN to PC2_OUT | tdis | 98 | ns | VCC = 4.5 V; -40 °C to +125 °C; CL = 50 pF | 15 | ||
| Transition time PC1_OUT, PC3_OUT, PCP_OUT | tt | 7 | 15 | ns | VCC = 4.5 V; 25 °C; CL = 50 pF | 15 | |
| Transition time PC1_OUT, PC3_OUT, PCP_OUT | tt | 22 | ns | VCC = 4.5 V; -40 °C to +125 °C; CL = 50 pF | 15 | ||
| Center frequency | f0 | 7 | 10 | MHz | VVCO_IN = 0.5VCC; duty cycle = 50 %; R1 = 3 kΩ; R2 = ∞ Ω; C1 = 40 pF; VCC = 3.0 V | 16 | |
| Center frequency | f0 | 11 | 17 | MHz | VVCO_IN = 0.5VCC; duty cycle = 50 %; R1 = 3 kΩ; R2 = ∞ Ω; C1 = 40 pF; VCC = 4.5 V | 16 | |
| Center frequency | f0 | 13 | 21 | MHz | VVCO_IN = 0.5VCC; duty cycle = 50 %; R1 = 3 kΩ; R2 = ∞ Ω; C1 = 40 pF; VCC = 6.0 V | 16 | |
| Duty cycle VCO_OUT | δ | 50 | % | VCO_OUT; VCC = 3.0 V to 6.0 V | 16 |
CAD (KiCad official)
- Symbol:
74HC4046APW-Q100J - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
74hc4046apw-q100j-etched.step/74hc4046apw-q100j-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc4046apw-q100j.step/74hc4046apw-q100j.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (32 pp, sha256
0219f6c13f5b2b9f, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).