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74HC4017D-Q100J
Public Made by Adomby adom
Nexperia Counters / Dividers, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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74HC4017D-Q100J
Nexperia · Counters / Dividers · SO-16
74HC4017D-Q100J from Nexperia, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q5 | output | Decoded output 5, goes HIGH when the counter is in state 5. |
| 2 | Q1 | output | Decoded output 1, goes HIGH when the counter is in state 1 and is LOW after reset. |
| 3 | Q0 | output | Decoded output 0, HIGH after a master reset (MR HIGH). |
| 4 | Q2 | output | Decoded output 2, goes HIGH when the counter is in state 2. |
| 5 | Q6 | output | Decoded output 6, goes HIGH when the counter is in state 6. |
| 6 | Q7 | output | Decoded output 7, goes HIGH when the counter is in state 7. |
| 7 | Q3 | output | Decoded output 3, goes HIGH when the counter is in state 3. |
| 8 | GND | power_in | Ground (0 V). |
| 9 | Q8 | output | Decoded output 8, goes HIGH when the counter is in state 8. |
| 10 | Q4 | output | Decoded output 4, goes HIGH when the counter is in state 4. |
| 11 | Q9 | output | Decoded output 9, goes HIGH when the counter is in state 9. |
| 12 | Q5-9 | output | Carry output (active LOW), LOW in counter states 5 to 9, and can drive CP0 of the next cascaded counter. |
| 13 | CP1 | input | Clock input, HIGH-to-LOW edge-triggered (counts while CP0 is HIGH). |
| 14 | CP0 | input | Clock input, LOW-to-HIGH edge-triggered (counts while CP1 is LOW). |
| 15 | MR | input | Master reset input (active HIGH), asynchronously resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW). |
| 16 | VCC | power_in | Supply voltage, 2.0 V to 6.0 V for 74HC4017-Q100 (4.5 V to 5.5 V for 74HCT). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SO-16 |
| Category | Logic ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 6 | ||
| Input clamping current | IIK | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V; printed ±20 | 6 | ||
| Output clamping current | IOK | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V; printed ±20 | 6 | ||
| Output current | IO | 25 | mA | -0.5 V < VO < VCC + 0.5 V; printed ±25 | 6 | ||
| Supply current | ICC | 50 | mA | 6 | |||
| Ground current | IGND | -50 | mA | 6 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 6 | ||
| Total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C; SO16 derates 12.4 mW/K above 110 °C | 6 | ||
| Supply voltage | VCC | 2 | 5 | 6 | V | 74HC4017-Q100 | 6 |
| Input voltage | VI | 0 | 6 | V | 0 to VCC | 6 | |
| Output voltage | VO | 0 | 6 | V | 0 to VCC | 6 | |
| Input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 6 | ||
| Input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 6 | |
| Input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 6 | ||
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 6 | |
| HIGH-level input voltage | VIH | 1.5 | V | VCC = 2.0 V; -40 °C to +125 °C | 7 | ||
| HIGH-level input voltage | VIH | 3.15 | V | VCC = 4.5 V; -40 °C to +125 °C | 7 | ||
| HIGH-level input voltage | VIH | 4.2 | V | VCC = 6.0 V; -40 °C to +125 °C | 7 | ||
| LOW-level input voltage | VIL | 0.5 | V | VCC = 2.0 V; -40 °C to +125 °C | 7 | ||
| LOW-level input voltage | VIL | 1.35 | V | VCC = 4.5 V; -40 °C to +125 °C | 7 | ||
| LOW-level input voltage | VIL | 1.8 | V | VCC = 6.0 V; -40 °C to +125 °C | 7 | ||
| HIGH-level output voltage | VOH | 1.9 | V | VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; -40 °C to +125 °C | 7 | ||
| HIGH-level output voltage | VOH | 4.4 | V | VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +125 °C | 7 | ||
| HIGH-level output voltage | VOH | 5.9 | V | VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; -40 °C to +125 °C | 7 | ||
| HIGH-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 7 | ||
| HIGH-level output voltage | VOH | 5.2 | V | VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; -40 °C to +125 °C | 7 | ||
| LOW-level output voltage | VOL | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C | 7 | ||
| LOW-level output voltage | VOL | 0.4 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 7 | ||
| Input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C; printed ±1.0 | 7 | |
| Supply current | ICC | 160 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 7 | ||
| Input capacitance | CI | 3.5 | pF | 25 °C | 7 | ||
| Propagation delay CP0 to Qn, Q5-9 | tpd | 345 | ns | VCC = 2.0 V; CL = 50 pF; -40 °C to +125 °C | 9 | ||
| Propagation delay CP0 to Qn, Q5-9 | tpd | 69 | ns | VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C | 9 | ||
| Propagation delay CP0 to Qn, Q5-9 | tpd | 59 | ns | VCC = 6.0 V; CL = 50 pF; -40 °C to +125 °C | 9 | ||
| Propagation delay CP1 to Qn, Q5-9 | tpd | 375 | ns | VCC = 2.0 V; CL = 50 pF; -40 °C to +125 °C | 9 | ||
| Propagation delay CP1 to Qn, Q5-9 | tpd | 75 | ns | VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C | 9 | ||
| Propagation delay CP1 to Qn, Q5-9 | tpd | 64 | ns | VCC = 6.0 V; CL = 50 pF; -40 °C to +125 °C | 9 | ||
| HIGH to LOW propagation delay MR to Qn | tPHL | 69 | ns | VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C | 9 | ||
| LOW to HIGH propagation delay MR to Q5-9, Q0 | tPLH | 69 | ns | VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C | 9 | ||
| Transition time | tt | 22 | ns | VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C | 9 | ||
| Pulse width CP0 and CP1 (HIGH or LOW) | tW | 24 | ns | VCC = 4.5 V; -40 °C to +125 °C | 9 | ||
| Pulse width MR (HIGH) | tW | 24 | ns | VCC = 4.5 V; -40 °C to +125 °C | 9 | ||
| Set-up time CP1 to CP0; CP0 to CP1 | tsu | 15 | ns | VCC = 4.5 V; -40 °C to +125 °C | 9 | ||
| Hold time CP1 to CP0; CP0 to CP1 | th | 15 | ns | VCC = 4.5 V; -40 °C to +125 °C | 10 | ||
| Recovery time MR to CP0 and MR to CP1 | trec | 5 | ns | VCC = 4.5 V; -40 °C to +125 °C | 10 | ||
| Maximum frequency CP0 or CP1 | fmax | 20 | MHz | VCC = 4.5 V; -40 °C to +125 °C | 10 | ||
| Power dissipation capacitance | CPD | 35 | pF | VI = GND to VCC; VCC = 5 V; fi = 1 MHz | 10 |
CAD (KiCad official)
- Symbol:
74HC4017D-Q100J - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files:
74hc4017d-q100j-etched.step/74hc4017d-q100j-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc4017d-q100j.step/74hc4017d-q100j.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (20 pp, sha256
a00ce818f18c2dca, retrieved 2026-10-27, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74HC4017D-Q100J
**Nexperia** · Counters / Dividers · SO-16
74HC4017D-Q100J from Nexperia, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q5 | output | Decoded output 5, goes HIGH when the counter is in state 5. |
| 2 | Q1 | output | Decoded output 1, goes HIGH when the counter is in state 1 and is LOW after reset. |
| 3 | Q0 | output | Decoded output 0, HIGH after a master reset (MR HIGH). |
| 4 | Q2 | output | Decoded output 2, goes HIGH when the counter is in state 2. |
| 5 | Q6 | output | Decoded output 6, goes HIGH when the counter is in state 6. |
| 6 | Q7 | output | Decoded output 7, goes HIGH when the counter is in state 7. |
| 7 | Q3 | output | Decoded output 3, goes HIGH when the counter is in state 3. |
| 8 | GND | power_in | Ground (0 V). |
| 9 | Q8 | output | Decoded output 8, goes HIGH when the counter is in state 8. |
| 10 | Q4 | output | Decoded output 4, goes HIGH when the counter is in state 4. |
| 11 | Q9 | output | Decoded output 9, goes HIGH when the counter is in state 9. |
| 12 | Q5-9 | output | Carry output (active LOW), LOW in counter states 5 to 9, and can drive CP0 of the next cascaded counter. |
| 13 | CP1 | input | Clock input, HIGH-to-LOW edge-triggered (counts while CP0 is HIGH). |
| 14 | CP0 | input | Clock input, LOW-to-HIGH edge-triggered (counts while CP1 is LOW). |
| 15 | MR | input | Master reset input (active HIGH), asynchronously resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW). |
| 16 | VCC | power_in | Supply voltage, 2.0 V to 6.0 V for 74HC4017-Q100 (4.5 V to 5.5 V for 74HCT). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SO-16 |
| Category | Logic ICs |
| Pins | 16 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | | 7 | V | | 6 |
| Input clamping current | IIK | | | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V; printed ±20 | 6 |
| Output clamping current | IOK | | | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V; printed ±20 | 6 |
| Output current | IO | | | 25 | mA | -0.5 V < VO < VCC + 0.5 V; printed ±25 | 6 |
| Supply current | ICC | | | 50 | mA | | 6 |
| Ground current | IGND | -50 | | | mA | | 6 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 6 |
| Total power dissipation | Ptot | | | 500 | mW | Tamb = -40 °C to +125 °C; SO16 derates 12.4 mW/K above 110 °C | 6 |
| Supply voltage | VCC | 2 | 5 | 6 | V | 74HC4017-Q100 | 6 |
| Input voltage | VI | 0 | | 6 | V | 0 to VCC | 6 |
| Output voltage | VO | 0 | | 6 | V | 0 to VCC | 6 |
| Input transition rise and fall rate | Δt/ΔV | | | 625 | ns/V | VCC = 2.0 V | 6 |
| Input transition rise and fall rate | Δt/ΔV | | 1.67 | 139 | ns/V | VCC = 4.5 V | 6 |
| Input transition rise and fall rate | Δt/ΔV | | | 83 | ns/V | VCC = 6.0 V | 6 |
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | | 6 |
| HIGH-level input voltage | VIH | 1.5 | | | V | VCC = 2.0 V; -40 °C to +125 °C | 7 |
| HIGH-level input voltage | VIH | 3.15 | | | V | VCC = 4.5 V; -40 °C to +125 °C | 7 |
| HIGH-level input voltage | VIH | 4.2 | | | V | VCC = 6.0 V; -40 °C to +125 °C | 7 |
| LOW-level input voltage | VIL | | | 0.5 | V | VCC = 2.0 V; -40 °C to +125 °C | 7 |
| LOW-level input voltage | VIL | | | 1.35 | V | VCC = 4.5 V; -40 °C to +125 °C | 7 |
| LOW-level input voltage | VIL | | | 1.8 | V | VCC = 6.0 V; -40 °C to +125 °C | 7 |
| HIGH-level output voltage | VOH | 1.9 | | | V | VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; -40 °C to +125 °C | 7 |
| HIGH-level output voltage | VOH | 4.4 | | | V | VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +125 °C | 7 |
| HIGH-level output voltage | VOH | 5.9 | | | V | VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; -40 °C to +125 °C | 7 |
| HIGH-level output voltage | VOH | 3.7 | | | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 7 |
| HIGH-level output voltage | VOH | 5.2 | | | V | VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; -40 °C to +125 °C | 7 |
| LOW-level output voltage | VOL | | | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C | 7 |
| LOW-level output voltage | VOL | | | 0.4 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 7 |
| Input leakage current | II | -1 | | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C; printed ±1.0 | 7 |
| Supply current | ICC | | | 160 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 7 |
| Input capacitance | CI | | 3.5 | | pF | 25 °C | 7 |
| Propagation delay CP0 to Qn, Q5-9 | tpd | | | 345 | ns | VCC = 2.0 V; CL = 50 pF; -40 °C to +125 °C | 9 |
| Propagation delay CP0 to Qn, Q5-9 | tpd | | | 69 | ns | VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C | 9 |
| Propagation delay CP0 to Qn, Q5-9 | tpd | | | 59 | ns | VCC = 6.0 V; CL = 50 pF; -40 °C to +125 °C | 9 |
| Propagation delay CP1 to Qn, Q5-9 | tpd | | | 375 | ns | VCC = 2.0 V; CL = 50 pF; -40 °C to +125 °C | 9 |
| Propagation delay CP1 to Qn, Q5-9 | tpd | | | 75 | ns | VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C | 9 |
| Propagation delay CP1 to Qn, Q5-9 | tpd | | | 64 | ns | VCC = 6.0 V; CL = 50 pF; -40 °C to +125 °C | 9 |
| HIGH to LOW propagation delay MR to Qn | tPHL | | | 69 | ns | VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C | 9 |
| LOW to HIGH propagation delay MR to Q5-9, Q0 | tPLH | | | 69 | ns | VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C | 9 |
| Transition time | tt | | | 22 | ns | VCC = 4.5 V; CL = 50 pF; -40 °C to +125 °C | 9 |
| Pulse width CP0 and CP1 (HIGH or LOW) | tW | 24 | | | ns | VCC = 4.5 V; -40 °C to +125 °C | 9 |
| Pulse width MR (HIGH) | tW | 24 | | | ns | VCC = 4.5 V; -40 °C to +125 °C | 9 |
| Set-up time CP1 to CP0; CP0 to CP1 | tsu | 15 | | | ns | VCC = 4.5 V; -40 °C to +125 °C | 9 |
| Hold time CP1 to CP0; CP0 to CP1 | th | 15 | | | ns | VCC = 4.5 V; -40 °C to +125 °C | 10 |
| Recovery time MR to CP0 and MR to CP1 | trec | 5 | | | ns | VCC = 4.5 V; -40 °C to +125 °C | 10 |
| Maximum frequency CP0 or CP1 | fmax | 20 | | | MHz | VCC = 4.5 V; -40 °C to +125 °C | 10 |
| Power dissipation capacitance | CPD | | 35 | | pF | VI = GND to VCC; VCC = 5 V; fi = 1 MHz | 10 |
## CAD (KiCad official)
- Symbol: `74HC4017D-Q100J`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files: `74hc4017d-q100j-etched.step` / `74hc4017d-q100j-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc4017d-q100j.step` / `74hc4017d-q100j.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74HC4017D-Q100J.pdf) (20 pp, sha256 `a00ce818f18c2dca`, retrieved 2026-10-27, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74hc4017d-q100j-datasheet.pdf)