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74HC40103D

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Nexperia Counters, Dividers, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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74HC40103D

Nexperia · Counters, Dividers · SOIC-16

74HC40103D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CP input Clock input, LOW-to-HIGH edge-triggered; counter is decremented by one on each positive-going transition; minimum pulse width 33 ns at VCC = 4.5 V.
2 MR input Asynchronous master reset input, active LOW; when LOW asynchronously clears counter to maximum count (decimal 255) regardless of the state of any other input; minimum pulse width 25 ns at VCC = 4.5 V.
3 TE input Terminal enable input, active LOW; counting is inhibited when HIGH; terminal count output TC goes LOW when count reaches zero only if TE is LOW.
4 P0 input Jam input 0 (least significant bit of the 8-bit preset word); clocked into counter on next positive-going CP when PE is LOW, or asynchronously forced in when PL is LOW.
5 P1 input Jam input 1; clocked into counter on next positive-going CP when PE is LOW, or asynchronously forced in when PL is LOW.
6 P2 input Jam input 2; clocked into counter on next positive-going CP when PE is LOW, or asynchronously forced in when PL is LOW.
7 P3 input Jam input 3; clocked into counter on next positive-going CP when PE is LOW, or asynchronously forced in when PL is LOW.
8 GND power_in Ground supply reference, 0 V.
9 PL input Asynchronous preset enable input, active LOW; when LOW asynchronously forces jam input data (P0-P7) into counter regardless of the state of PE, TE, or CP.
10 P4 input Jam input 4; clocked into counter on next positive-going CP when PE is LOW, or asynchronously forced in when PL is LOW.
11 P5 input Jam input 5; clocked into counter on next positive-going CP when PE is LOW, or asynchronously forced in when PL is LOW.
12 P6 input Jam input 6; clocked into counter on next positive-going CP when PE is LOW, or asynchronously forced in when PL is LOW. (Datasheet Table 2 erroneously prints symbol as P5; pinning diagram and functional diagram confirm this is P6.)
13 P7 input Jam input 7 (most significant bit of the 8-bit preset word); clocked into counter on next positive-going CP when PE is LOW, or asynchronously forced in when PL is LOW.
14 TC output Terminal count output, active LOW; goes LOW when count reaches zero and TE is LOW, and remains LOW for one full clock period; maximum propagation delay from CP is 60 ns at VCC = 4.5 V.
15 PE input Synchronous preset enable input, active LOW; when LOW data at jam inputs (P0-P7) is clocked into counter on next positive-going clock transition regardless of TE state; set-up time before CP minimum 15 ns at VCC = 4.5 V.
16 VCC power_in Positive supply voltage; recommended operating range 2.0 V to 6.0 V; absolute maximum +7 V; quiescent ICC max 8.0 µA at VCC = 6.0 V (25 °C).

Key specifications

Parameter Value
Manufacturer Nexperia
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: 74HC40103D
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: 74hc40103d-etched.step / 74hc40103d-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc40103d.step / 74hc40103d.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (21 pp, sha256 8f1087cf72227e26, retrieved 2026-09-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF