component
74HC390D
Public Made by Adomby adom
Nexperia Counters, Dividers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HC390D
Nexperia · Counters, Dividers · SOIC-16
74HC390D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1CP0 | input | Clock input of the divide-by-2 section, triggered on the HIGH-to-LOW (edge-triggered) transition. |
| 2 | 1MR | input | Asynchronous master reset input, active HIGH; a HIGH overrides the clocks and sets the four outputs LOW. |
| 3 | 1Q0 | output | Flip-flop output Q0 of the first counter; it is connected to 1CP1 in BCD decade operation and is the decade output in bi-quinary operation. |
| 4 | 1CP1 | input | Clock input of the divide-by-5 section, triggered on the HIGH-to-LOW (edge-triggered) transition. |
| 5 | 1Q1 | output | Flip-flop output Q1 of the first counter. |
| 6 | 1Q2 | output | Flip-flop output Q2 of the first counter. |
| 7 | 1Q3 | output | Flip-flop output Q3 of the first counter; it is connected to 1CP0 in bi-quinary operation. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages. |
| 9 | 2Q3 | output | Flip-flop output Q3 of the second counter; it is connected to 2CP0 in bi-quinary operation. |
| 10 | 2Q2 | output | Flip-flop output Q2 of the second counter. |
| 11 | 2Q1 | output | Flip-flop output Q1 of the second counter. |
| 12 | 2CP1 | input | Clock input of the divide-by-5 section, triggered on the HIGH-to-LOW (edge-triggered) transition. |
| 13 | 2Q0 | output | Flip-flop output Q0 of the second counter; it is connected to 2CP1 in BCD decade operation and is the decade output in bi-quinary operation. |
| 14 | 2MR | input | Asynchronous master reset input, active HIGH; a HIGH overrides the clocks and sets the four outputs LOW. |
| 15 | 2CP0 | input | Clock input of the divide-by-2 section, triggered on the HIGH-to-LOW (edge-triggered) transition. |
| 16 | VCC | power_in | Supply voltage; recommended range is 2.0 V to 6.0 V for 74HC390 and 4.5 V to 5.5 V for 74HCT390, with an absolute maximum of +7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SOIC-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage (absolute maximum) | VCC | -0.5 | 7 | V | 4 | ||
| Input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 4 | |
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 4 | |
| Output current | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 4 | |
| Supply current | ICC | 50 | mA | 4 | |||
| Ground current | IGND | -50 | mA | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Total power dissipation | Ptot | 500 | mW | SOT109-1 (SO16); derates 12.4 mW/K above 110 °C | 4 | ||
| Supply voltage (recommended) | VCC | 2 | 5 | 6 | V | 74HC390 | 4 |
| Input voltage (recommended) | VI | 0 | V | 74HC390; max printed as VCC | 4 | ||
| Output voltage (recommended) | VO | 0 | V | 74HC390; max printed as VCC | 4 | ||
| Ambient temperature | Tamb | -40 | 25 | 125 | °C | 74HC390 | 4 |
| Input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC = 2.0 V | 4 | ||
| Input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 4 | |
| Input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC = 6.0 V | 4 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | VCC = 2.0 V; 25 °C | 4 | |
| HIGH-level input voltage | VIH | 1.5 | V | VCC = 2.0 V; -40 °C to +125 °C | 4 | ||
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | VCC = 4.5 V; 25 °C | 4 | |
| HIGH-level input voltage | VIH | 3.15 | V | VCC = 4.5 V; -40 °C to +125 °C | 4 | ||
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | VCC = 6.0 V; 25 °C | 4 | |
| HIGH-level input voltage | VIH | 4.2 | V | VCC = 6.0 V; -40 °C to +125 °C | 4 | ||
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | VCC = 2.0 V; 25 °C | 4 | |
| LOW-level input voltage | VIL | 0.5 | V | VCC = 2.0 V; -40 °C to +125 °C | 4 | ||
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | VCC = 4.5 V; 25 °C | 4 | |
| LOW-level input voltage | VIL | 1.35 | V | VCC = 4.5 V; -40 °C to +125 °C | 4 | ||
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | VCC = 6.0 V; 25 °C | 4 | |
| LOW-level input voltage | VIL | 1.8 | V | VCC = 6.0 V; -40 °C to +125 °C | 4 | ||
| HIGH-level output voltage | VOH | 1.9 | 2 | V | VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; 25 °C | 5 | |
| HIGH-level output voltage | VOH | 1.9 | V | VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; -40 °C to +125 °C | 5 | ||
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; 25 °C | 5 | |
| HIGH-level output voltage | VOH | 4.4 | V | VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; -40 °C to +125 °C | 5 | ||
| HIGH-level output voltage | VOH | 5.9 | 6 | V | VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; 25 °C | 5 | |
| HIGH-level output voltage | VOH | 5.9 | V | VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; -40 °C to +125 °C | 5 | ||
| HIGH-level output voltage | VOH | 3.98 | 4.32 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; 25 °C | 5 | |
| HIGH-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 5 | ||
| HIGH-level output voltage | VOH | 5.48 | 5.81 | V | VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; 25 °C | 5 | |
| HIGH-level output voltage | VOH | 5.2 | V | VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; -40 °C to +125 °C | 5 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; 25 °C | 5 | |
| LOW-level output voltage | VOL | 0.1 | V | VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; -40 °C to +125 °C | 5 | ||
| LOW-level output voltage | VOL | 0.15 | 0.26 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; 25 °C | 5 | |
| LOW-level output voltage | VOL | 0.4 | V | VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; -40 °C to +125 °C | 5 | ||
| LOW-level output voltage | VOL | 0.16 | 0.26 | V | VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; 25 °C | 5 | |
| Input leakage current | II | -0.1 | 0.1 | μA | VI = VCC or GND; VCC = 6.0 V; 25 °C | 5 | |
| Input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 6.0 V; -40 °C to +125 °C | 5 | |
| Supply current | ICC | 8 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; 25 °C | 5 | ||
| Supply current | ICC | 160 | μA | VI = VCC or GND; IO = 0 A; VCC = 6.0 V; -40 °C to +125 °C | 5 | ||
| Propagation delay nCP0 to nQ0 | tpd | 44 | ns | VCC = 4.5 V; -40 °C to +125 °C; see Fig. 5; CL = 50 pF | 6 | ||
| Propagation delay nCP1 to nQ1 | tpd | 47 | ns | VCC = 4.5 V; -40 °C to +125 °C; see Fig. 5; CL = 50 pF | 6 | ||
| Propagation delay nCP1 to nQ2 | tpd | 63 | ns | VCC = 4.5 V; -40 °C to +125 °C; see Fig. 5; CL = 50 pF | 6 | ||
| Propagation delay nMR to nQn | tPHL | 50 | ns | VCC = 4.5 V; -40 °C to +125 °C; see Fig. 6; CL = 50 pF | 6 | ||
| Transition time nQn | tt | 22 | ns | VCC = 4.5 V; -40 °C to +125 °C; see Fig. 5 | 6 | ||
| Pulse width nCP0, nCP1 HIGH or LOW | tW | 24 | ns | VCC = 4.5 V; -40 °C to +125 °C; see Fig. 5 | 7 | ||
| Pulse width nMR HIGH | tW | 26 | ns | VCC = 4.5 V; -40 °C to +125 °C; see Fig. 6 | 7 | ||
| Recovery time nMR to nCPn | trec | 22 | ns | VCC = 4.5 V; -40 °C to +125 °C; see Fig. 6 | 7 | ||
| Maximum frequency nCPn | fmax | 20 | MHz | VCC = 4.5 V; -40 °C to +125 °C; see Fig. 5 | 7 |
CAD (KiCad official)
- Symbol:
74HC390D - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
74hc390d-etched.step/74hc390d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc390d.step/74hc390d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (15 pp, sha256
90573abe40d0d6f5, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).