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74HC377PW

Public Made by Adom

by adom

Nexperia Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC377PW

Nexperia · Flip Flops · TSSOP-20

74HC377PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 E input Active-LOW data enable input; it must be stable one set-up time before the LOW-to-HIGH CP transition for predictable operation, and when E is HIGH the outputs do not change.
2 Q0 output Flip-flop output 0 that takes the state of D0 on the LOW-to-HIGH CP edge when E is LOW; output current must not exceed ±25 mA (absolute maximum).
3 D0 input Data input 0 sampled on the LOW-to-HIGH CP transition, with clamp diodes that allow current-limited interfacing to voltages above VCC (input clamping current ±20 mA).
4 D1 input Data input 1 sampled on the LOW-to-HIGH CP transition, with clamp diodes that allow current-limited interfacing to voltages above VCC (input clamping current ±20 mA).
5 Q1 output Flip-flop output 1 that takes the state of D1 on the LOW-to-HIGH CP edge when E is LOW; output current must not exceed ±25 mA (absolute maximum).
6 Q2 output Flip-flop output 2 that takes the state of D2 on the LOW-to-HIGH CP edge when E is LOW; output current must not exceed ±25 mA (absolute maximum).
7 D2 input Data input 2 sampled on the LOW-to-HIGH CP transition, with clamp diodes that allow current-limited interfacing to voltages above VCC (input clamping current ±20 mA).
8 D3 input Data input 3 sampled on the LOW-to-HIGH CP transition, with clamp diodes that allow current-limited interfacing to voltages above VCC (input clamping current ±20 mA).
9 Q3 output Flip-flop output 3 that takes the state of D3 on the LOW-to-HIGH CP edge when E is LOW; output current must not exceed ±25 mA (absolute maximum).
10 GND power_in Ground (0 V) reference for all voltages in the device.
11 CP input Clock input that is positive-edge triggered on the LOW-to-HIGH transition; Dn and E must meet set-up and hold times around this edge.
12 Q4 output Flip-flop output 4 that takes the state of D4 on the LOW-to-HIGH CP edge when E is LOW; output current must not exceed ±25 mA (absolute maximum).
13 D4 input Data input 4 sampled on the LOW-to-HIGH CP transition, with clamp diodes that allow current-limited interfacing to voltages above VCC (input clamping current ±20 mA).
14 D5 input Data input 5 sampled on the LOW-to-HIGH CP transition, with clamp diodes that allow current-limited interfacing to voltages above VCC (input clamping current ±20 mA).
15 Q5 output Flip-flop output 5 that takes the state of D5 on the LOW-to-HIGH CP edge when E is LOW; output current must not exceed ±25 mA (absolute maximum).
16 Q6 output Flip-flop output 6 that takes the state of D6 on the LOW-to-HIGH CP edge when E is LOW; output current must not exceed ±25 mA (absolute maximum).
17 D6 input Data input 6 sampled on the LOW-to-HIGH CP transition, with clamp diodes that allow current-limited interfacing to voltages above VCC (input clamping current ±20 mA).
18 D7 input Data input 7 sampled on the LOW-to-HIGH CP transition, with clamp diodes that allow current-limited interfacing to voltages above VCC (input clamping current ±20 mA).
19 Q7 output Flip-flop output 7 that takes the state of D7 on the LOW-to-HIGH CP edge when E is LOW; output current must not exceed ±25 mA (absolute maximum).
20 VCC power_in Supply voltage: 2.0 V to 6.0 V for 74HC377 and 4.5 V to 5.5 V for 74HCT377 (absolute maximum +7 V).

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VCC -0.5 7 V 4
input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 4
supply current ICC 50 mA 4
ground current IGND -50 mA 4
storage temperature Tstg -65 150 °C 4
total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
supply voltage VCC 2 5 6 V 4
input voltage VI 0 V 4
output voltage VO 0 V 4
ambient temperature Tamb -40 125 °C 4
input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 4
input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 4
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V; min/max -40 °C to +125 °C, typ 25 °C 5
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V; min/max -40 °C to +125 °C, typ 25 °C 5
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V; min/max -40 °C to +125 °C, typ 25 °C 5
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V; min/max -40 °C to +125 °C, typ 25 °C 5
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V; min/max -40 °C to +125 °C, typ 25 °C 5
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V; min/max -40 °C to +125 °C, typ 25 °C 5
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; min/max -40 °C to +125 °C, typ 25 °C 5
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; min/max -40 °C to +125 °C, typ 25 °C 5
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; min/max -40 °C to +125 °C, typ 25 °C 5
HIGH-level output voltage VOH 3.7 4.32 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; min/max -40 °C to +125 °C, typ 25 °C 5
HIGH-level output voltage VOH 5.2 5.81 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; min/max -40 °C to +125 °C, typ 25 °C 5
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; min/max -40 °C to +125 °C, typ 25 °C 5
LOW-level output voltage VOL 0.15 0.4 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; min/max -40 °C to +125 °C, typ 25 °C 5
LOW-level output voltage VOL 0.16 0.4 V VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; min/max -40 °C to +125 °C, typ 25 °C 5
input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V; min/max -40 °C to +125 °C 5
supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; max -40 °C to +125 °C 5
propagation delay CP to Qn tpd 44 240 ns CP to Qn; see Fig. 6; VCC = 2.0 V; CL = 50 pF; max -40 °C to +125 °C, typ 25 °C 7
propagation delay CP to Qn tpd 16 48 ns CP to Qn; see Fig. 6; VCC = 4.5 V; CL = 50 pF; max -40 °C to +125 °C, typ 25 °C 7
propagation delay CP to Qn tpd 13 41 ns CP to Qn; see Fig. 6; VCC = 6.0 V; CL = 50 pF; max -40 °C to +125 °C, typ 25 °C 7
transition time Qn output tt 19 110 ns Qn output; see Fig. 6; VCC = 2.0 V; CL = 50 pF; max -40 °C to +125 °C, typ 25 °C 7
transition time Qn output tt 7 22 ns Qn output; see Fig. 6; VCC = 4.5 V; CL = 50 pF; max -40 °C to +125 °C, typ 25 °C 7
transition time Qn output tt 6 19 ns Qn output; see Fig. 6; VCC = 6.0 V; CL = 50 pF; max -40 °C to +125 °C, typ 25 °C 7
pulse width tW 120 14 ns CP input HIGH or LOW; see Fig. 6; VCC = 2.0 V; min -40 °C to +125 °C, typ 25 °C 7
pulse width tW 24 5 ns CP input HIGH or LOW; see Fig. 6; VCC = 4.5 V; min -40 °C to +125 °C, typ 25 °C 7
pulse width tW 20 4 ns CP input HIGH or LOW; see Fig. 6; VCC = 6.0 V; min -40 °C to +125 °C, typ 25 °C 7
set-up time Dn to CP tsu 90 14 ns Dn to CP; see Fig. 7; VCC = 2.0 V; min -40 °C to +125 °C, typ 25 °C 7
set-up time Dn to CP tsu 18 5 ns Dn to CP; see Fig. 7; VCC = 4.5 V; min -40 °C to +125 °C, typ 25 °C 7
set-up time Dn to CP tsu 15 4 ns Dn to CP; see Fig. 7; VCC = 6.0 V; min -40 °C to +125 °C, typ 25 °C 7
set-up time E to CP tsu 90 6 ns E to CP; see Fig. 7; VCC = 2.0 V; min -40 °C to +125 °C, typ 25 °C 7
set-up time E to CP tsu 18 2 ns E to CP; see Fig. 7; VCC = 4.5 V; min -40 °C to +125 °C, typ 25 °C 7
set-up time E to CP tsu 15 2 ns E to CP; see Fig. 7; VCC = 6.0 V; min -40 °C to +125 °C, typ 25 °C 7
hold time Dn to CP th 3 -8 ns Dn to CP; see Fig. 7; VCC = 2.0 V; min -40 °C to +125 °C, typ 25 °C 7
hold time Dn to CP th 3 -3 ns Dn to CP; see Fig. 7; VCC = 4.5 V; min -40 °C to +125 °C, typ 25 °C 7
hold time Dn to CP th 3 -2 ns Dn to CP; see Fig. 7; VCC = 6.0 V; min -40 °C to +125 °C, typ 25 °C 7
hold time E to CP th 4 -3 ns E to CP; see Fig. 7; VCC = 2.0 V; min -40 °C to +125 °C, typ 25 °C 7
hold time E to CP th 4 -1 ns E to CP; see Fig. 7; VCC = 4.5 V; min -40 °C to +125 °C, typ 25 °C 7
maximum frequency fmax 4 23 MHz CP input; see Fig. 6; VCC = 2.0 V; min -40 °C to +125 °C, typ 25 °C 7
maximum frequency fmax 20 70 MHz CP input; see Fig. 6; VCC = 4.5 V; min -40 °C to +125 °C, typ 25 °C 7
maximum frequency fmax 24 83 MHz CP input; see Fig. 6; VCC = 6.0 V; min -40 °C to +125 °C, typ 25 °C 7

CAD (KiCad official)

  • Symbol: 74HC377PW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74hc377pw-etched.step / 74hc377pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc377pw.step / 74hc377pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 d3e6848eadc38fcc, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF