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74HC377PW-Q100J

Public Made by Adom

by adom

Nexperia Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC377PW-Q100J

Nexperia · Flip Flops · TSSOP-20

74HC377PW-Q100J from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 E input Data enable input (active LOW): when LOW, the outputs Qn take the state of their Dn inputs that meet set-up and hold time on the LOW-to-HIGH CP transition, and E must be stable one set-up time before that transition.
2 Q0 output Flip-flop output 0.
3 D0 input Data input 0, sampled on the LOW-to-HIGH clock transition when E is LOW; inputs include clamp diodes that allow current-limited interfacing to voltages above VCC.
4 D1 input Data input 1, sampled on the LOW-to-HIGH clock transition when E is LOW; inputs include clamp diodes that allow current-limited interfacing to voltages above VCC.
5 Q1 output Flip-flop output 1.
6 Q2 output Flip-flop output 2.
7 D2 input Data input 2, sampled on the LOW-to-HIGH clock transition when E is LOW; inputs include clamp diodes that allow current-limited interfacing to voltages above VCC.
8 D3 input Data input 3, sampled on the LOW-to-HIGH clock transition when E is LOW; inputs include clamp diodes that allow current-limited interfacing to voltages above VCC.
9 Q3 output Flip-flop output 3.
10 GND power_in Ground (0 V).
11 CP input Clock input, edge triggered on the LOW-to-HIGH transition; common clock for all eight flip-flops.
12 Q4 output Flip-flop output 4.
13 D4 input Data input 4, sampled on the LOW-to-HIGH clock transition when E is LOW; inputs include clamp diodes that allow current-limited interfacing to voltages above VCC.
14 D5 input Data input 5, sampled on the LOW-to-HIGH clock transition when E is LOW; inputs include clamp diodes that allow current-limited interfacing to voltages above VCC.
15 Q5 output Flip-flop output 5.
16 Q6 output Flip-flop output 6.
17 D6 input Data input 6, sampled on the LOW-to-HIGH clock transition when E is LOW; inputs include clamp diodes that allow current-limited interfacing to voltages above VCC.
18 D7 input Data input 7, sampled on the LOW-to-HIGH clock transition when E is LOW; inputs include clamp diodes that allow current-limited interfacing to voltages above VCC.
19 Q7 output Flip-flop output 7.
20 VCC power_in Supply voltage; recommended range 2.0 V to 6.0 V for 74HC377-Q100 and 4.5 V to 5.5 V for 74HCT377-Q100, with absolute maximum of +7 V.

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 2 5 6 V 4
Input voltage VI 0 V 4
Output voltage VO 0 V 4
Ambient temperature Tamb -40 125 °C 4
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 4
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 4
Supply voltage VCC -0.5 7 V 4
Input clamping current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamping current IOK -20 20 mA VO < -0.5 V or VO > VCC + 0.5 V 4
Output current IO -25 25 mA -0.5 V < VO < VCC + 0.5 V 4
Supply current ICC 50 mA 4
Ground current IGND -50 mA 4
Storage temperature Tstg -65 150 °C 4
Total power dissipation Ptot 500 mW Tamb = -40 °C to +125 °C 4
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V; Tamb -40 °C to +85 °C; typ at 25 °C 5
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V; Tamb -40 °C to +85 °C; typ at 25 °C 5
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V; Tamb -40 °C to +85 °C; typ at 25 °C 5
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V; Tamb -40 °C to +85 °C; typ at 25 °C 5
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V; Tamb -40 °C to +85 °C; typ at 25 °C 5
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V; Tamb -40 °C to +85 °C; typ at 25 °C 5
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; Tamb -40 °C to +85 °C; typ at 25 °C 5
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; Tamb -40 °C to +85 °C; typ at 25 °C 5
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; Tamb -40 °C to +85 °C; typ at 25 °C 5
HIGH-level output voltage VOH 3.84 4.32 V VI = VIH or VIL; IO = -4.0 mA; VCC = 4.5 V; Tamb -40 °C to +85 °C; typ at 25 °C 5
HIGH-level output voltage VOH 5.34 5.81 V VI = VIH or VIL; IO = -5.2 mA; VCC = 6.0 V; Tamb -40 °C to +85 °C; typ at 25 °C 5
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; Tamb -40 °C to +85 °C; typ at 25 °C 5
LOW-level output voltage VOL 0.15 0.33 V VI = VIH or VIL; IO = 4.0 mA; VCC = 4.5 V; Tamb -40 °C to +85 °C; typ at 25 °C 5
LOW-level output voltage VOL 0.16 0.33 V VI = VIH or VIL; IO = 5.2 mA; VCC = 6.0 V; Tamb -40 °C to +85 °C; typ at 25 °C 5
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V; Tamb -40 °C to +85 °C 5
Supply current ICC 80 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; Tamb -40 °C to +85 °C 5
CP to Qn propagation delay tpd 44 200 ns VCC = 2.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 6 7
CP to Qn propagation delay tpd 16 40 ns VCC = 4.5 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 6 7
CP to Qn propagation delay tpd 13 34 ns VCC = 6.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 6 7
Qn output transition time tt 19 95 ns VCC = 2.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 6 7
Qn output transition time tt 7 19 ns VCC = 4.5 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 6 7
Qn output transition time tt 6 16 ns VCC = 6.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 6 7
CP pulse width HIGH or LOW tW 100 14 ns VCC = 2.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 6 7
CP pulse width HIGH or LOW tW 20 5 ns VCC = 4.5 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 6 7
CP pulse width HIGH or LOW tW 17 4 ns VCC = 6.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 6 7
Dn data set-up time to CP tsu 75 14 ns VCC = 2.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 7 7
Dn data set-up time to CP tsu 15 5 ns VCC = 4.5 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 7 7
Dn data set-up time to CP tsu 13 4 ns VCC = 6.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 7 7
E enable set-up time to CP tsu 75 6 ns VCC = 2.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 7 7
E enable set-up time to CP tsu 15 2 ns VCC = 4.5 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 7 7
E enable set-up time to CP tsu 13 2 ns VCC = 6.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 7 7
Dn data hold time from CP th 3 -8 ns VCC = 2.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 7 7
Dn data hold time from CP th 3 -3 ns VCC = 4.5 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 7 7
Dn data hold time from CP th 3 -2 ns VCC = 6.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 7 7
E enable hold time from CP th 4 -3 ns VCC = 2.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 7 7
E enable hold time from CP th 4 -1 ns VCC = 4.5 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 7 7
Maximum clock frequency fmax 5 23 MHz VCC = 2.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 6 7
Maximum clock frequency fmax 24 70 MHz VCC = 4.5 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 6 7
Maximum clock frequency fmax 28 83 MHz VCC = 6.0 V; CL = 50 pF; Tamb -40 °C to +85 °C; typ at 25 °C; see Fig. 6 7

CAD (KiCad official)

  • Symbol: 74HC377PW-Q100J
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74hc377pw-q100j-etched.step / 74hc377pw-q100j-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc377pw-q100j.step / 74hc377pw-q100j.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 d015fe837c9c9606, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF