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74HC374PW

Public Made by Adom

by adom

Nexperia Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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74HC374PW

Nexperia · Flip Flops · TSSOP-20

74HC374PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-LOW common 3-state output enable; a HIGH level forces all Qn outputs to the high-impedance OFF-state without changing the flip-flop contents.
2 Q0 tri_state Non-inverting 3-state data output of flip-flop 0, which is high-impedance when OE is HIGH and rated for an output current of ±35 mA.
3 D0 input Data input to flip-flop 0, which must meet the set-up and hold times around the LOW-to-HIGH CP transition and may exceed VCC only through a current-limiting resistor because of its clamp diodes.
4 D1 input Data input to flip-flop 1, which must meet the set-up and hold times around the LOW-to-HIGH CP transition and may exceed VCC only through a current-limiting resistor because of its clamp diodes.
5 Q1 tri_state Non-inverting 3-state data output of flip-flop 1, which is high-impedance when OE is HIGH and rated for an output current of ±35 mA.
6 Q2 tri_state Non-inverting 3-state data output of flip-flop 2, which is high-impedance when OE is HIGH and rated for an output current of ±35 mA.
7 D2 input Data input to flip-flop 2, which must meet the set-up and hold times around the LOW-to-HIGH CP transition and may exceed VCC only through a current-limiting resistor because of its clamp diodes.
8 D3 input Data input to flip-flop 3, which must meet the set-up and hold times around the LOW-to-HIGH CP transition and may exceed VCC only through a current-limiting resistor because of its clamp diodes.
9 Q3 tri_state Non-inverting 3-state data output of flip-flop 3, which is high-impedance when OE is HIGH and rated for an output current of ±35 mA.
10 GND power_in Ground reference (0 V) for all voltages in the device.
11 CP input Clock input; the flip-flops store their D inputs on the LOW-to-HIGH (rising) edge of CP.
12 Q4 tri_state Non-inverting 3-state data output of flip-flop 4, which is high-impedance when OE is HIGH and rated for an output current of ±35 mA.
13 D4 input Data input to flip-flop 4, which must meet the set-up and hold times around the LOW-to-HIGH CP transition and may exceed VCC only through a current-limiting resistor because of its clamp diodes.
14 D5 input Data input to flip-flop 5, which must meet the set-up and hold times around the LOW-to-HIGH CP transition and may exceed VCC only through a current-limiting resistor because of its clamp diodes.
15 Q5 tri_state Non-inverting 3-state data output of flip-flop 5, which is high-impedance when OE is HIGH and rated for an output current of ±35 mA.
16 Q6 tri_state Non-inverting 3-state data output of flip-flop 6, which is high-impedance when OE is HIGH and rated for an output current of ±35 mA.
17 D6 input Data input to flip-flop 6, which must meet the set-up and hold times around the LOW-to-HIGH CP transition and may exceed VCC only through a current-limiting resistor because of its clamp diodes.
18 D7 input Data input to flip-flop 7, which must meet the set-up and hold times around the LOW-to-HIGH CP transition and may exceed VCC only through a current-limiting resistor because of its clamp diodes.
19 Q7 tri_state Non-inverting 3-state data output of flip-flop 7, which is high-impedance when OE is HIGH and rated for an output current of ±35 mA.
20 VCC power_in Supply voltage, 2.0 V to 6.0 V for the 74HC374 (absolute maximum −0.5 V to +7 V).

Key specifications

Parameter Value
Manufacturer Nexperia
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC (absolute maximum) VCC -0.5 7 V Voltages referenced to GND 4
Input clamping current IIK 20 mA VI < -0.5 V or VI > VCC + 0.5 V; printed as ±20 mA 4
Output clamping current IOK 20 mA VO < -0.5 V or VO > VCC + 0.5 V; printed as ±20 mA 4
Output current IO 35 mA -0.5 V < VO < VCC + 0.5 V; printed as ±35 mA 4
Supply current ICC 70 mA 4
Ground current IGND -70 mA 4
Storage temperature Tstg -65 150 °C 4
Total power dissipation Ptot 500 mW SOT360-1 (TSSOP20) derates linearly 10.0 mW/K above 100 °C 4
Supply voltage VCC (recommended) VCC 2 5 6 V 74HC374 column 4
Input voltage (recommended) VI 0 V Maximum printed as VCC 4
Output voltage (recommended) VO 0 V Maximum printed as VCC 4
Input transition rise and fall rate Δt/ΔV 625 ns/V VCC = 2.0 V 4
Input transition rise and fall rate Δt/ΔV 1.67 139 ns/V VCC = 4.5 V 4
Input transition rise and fall rate Δt/ΔV 83 ns/V VCC = 6.0 V 4
Ambient temperature Tamb -40 25 125 °C 74HC374 column 4
HIGH-level input voltage VIH 1.5 1.2 V VCC = 2.0 V; typ at Tamb 25 °C, min at -40 to +125 °C 5
HIGH-level input voltage VIH 3.15 2.4 V VCC = 4.5 V; typ at Tamb 25 °C, min at -40 to +125 °C 5
HIGH-level input voltage VIH 4.2 3.2 V VCC = 6.0 V; typ at Tamb 25 °C, min at -40 to +125 °C 5
LOW-level input voltage VIL 0.8 0.5 V VCC = 2.0 V; typ at Tamb 25 °C, max at -40 to +125 °C 5
LOW-level input voltage VIL 2.1 1.35 V VCC = 4.5 V; typ at Tamb 25 °C, max at -40 to +125 °C 5
LOW-level input voltage VIL 2.8 1.8 V VCC = 6.0 V; typ at Tamb 25 °C, max at -40 to +125 °C 5
HIGH-level output voltage VOH 1.9 2 V VI = VIH or VIL; IO = -20 μA; VCC = 2.0 V; typ at 25 °C, min at -40 to +125 °C 5
HIGH-level output voltage VOH 4.4 4.5 V VI = VIH or VIL; IO = -20 μA; VCC = 4.5 V; typ at 25 °C, min at -40 to +125 °C 5
HIGH-level output voltage VOH 5.9 6 V VI = VIH or VIL; IO = -20 μA; VCC = 6.0 V; typ at 25 °C, min at -40 to +125 °C 5
HIGH-level output voltage VOH 3.7 4.32 V VI = VIH or VIL; IO = -6.0 mA; VCC = 4.5 V; typ at 25 °C, min at -40 to +125 °C 5
HIGH-level output voltage VOH 5.2 5.81 V VI = VIH or VIL; IO = -7.8 mA; VCC = 6.0 V; typ at 25 °C, min at -40 to +125 °C 5
LOW-level output voltage VOL 0 0.1 V VI = VIH or VIL; IO = 20 μA; VCC = 2.0 V; typ at 25 °C, max at -40 to +125 °C 5
LOW-level output voltage VOL 0.15 0.4 V VI = VIH or VIL; IO = 6.0 mA; VCC = 4.5 V; typ at 25 °C, max at -40 to +125 °C 5
LOW-level output voltage VOL 0.16 0.4 V VI = VIH or VIL; IO = 7.8 mA; VCC = 6.0 V; typ at 25 °C, max at -40 to +125 °C 5
Input leakage current II -1 1 μA VI = VCC or GND; VCC = 6.0 V; limits at -40 to +125 °C (printed ±1.0) 5
OFF-state output current IOZ -10 10 μA VI = VIH or VIL; VCC = 6.0 V; VO = VCC or GND; limits at -40 to +125 °C (printed ±10) 5
Supply current ICC 160 μA VI = VCC or GND; IO = 0 A; VCC = 6.0 V; max at -40 to +125 °C 5
Propagation delay CP to Qn tpd 50 250 ns VCC = 2.0 V; see Fig. 7; typ at 25 °C, max at -40 to +125 °C 7
Propagation delay CP to Qn tpd 18 50 ns VCC = 4.5 V; see Fig. 7; typ at 25 °C, max at -40 to +125 °C 7
Propagation delay CP to Qn tpd 14 43 ns VCC = 6.0 V; see Fig. 7; typ at 25 °C, max at -40 to +125 °C 7
Enable time OE to Qn ten 41 225 ns VCC = 2.0 V; see Fig. 8; typ at 25 °C, max at -40 to +125 °C 7
Enable time OE to Qn ten 15 45 ns VCC = 4.5 V; see Fig. 8; typ at 25 °C, max at -40 to +125 °C 7
Enable time OE to Qn ten 12 38 ns VCC = 6.0 V; see Fig. 8; typ at 25 °C, max at -40 to +125 °C 7
Disable time OE to Qn tdis 50 225 ns VCC = 2.0 V; see Fig. 8; typ at 25 °C, max at -40 to +125 °C 7
Disable time OE to Qn tdis 18 45 ns VCC = 4.5 V; see Fig. 8; typ at 25 °C, max at -40 to +125 °C 7
Disable time OE to Qn tdis 14 38 ns VCC = 6.0 V; see Fig. 8; typ at 25 °C, max at -40 to +125 °C 7
Transition time Qn tt 14 90 ns VCC = 2.0 V; see Fig. 7; typ at 25 °C, max at -40 to +125 °C 7
Transition time Qn tt 5 18 ns VCC = 4.5 V; see Fig. 7; typ at 25 °C, max at -40 to +125 °C 7
Transition time Qn tt 4 15 ns VCC = 6.0 V; see Fig. 7; typ at 25 °C, max at -40 to +125 °C 7
Pulse width CP HIGH or LOW tW 120 19 ns VCC = 2.0 V; see Fig. 7; typ at 25 °C, min at -40 to +125 °C 7
Pulse width CP HIGH or LOW tW 24 7 ns VCC = 4.5 V; see Fig. 7; typ at 25 °C, min at -40 to +125 °C 7
Pulse width CP HIGH or LOW tW 20 6 ns VCC = 6.0 V; see Fig. 7; typ at 25 °C, min at -40 to +125 °C 7
Set-up time Dn to CP tsu 90 14 ns VCC = 2.0 V; see Fig. 7; typ at 25 °C, min at -40 to +125 °C 7
Set-up time Dn to CP tsu 18 5 ns VCC = 4.5 V; see Fig. 7; typ at 25 °C, min at -40 to +125 °C 7
Set-up time Dn to CP tsu 15 4 ns VCC = 6.0 V; see Fig. 7; typ at 25 °C, min at -40 to +125 °C 7
Hold time Dn to CP th 5 -6 ns VCC = 2.0 V; see Fig. 7; typ at 25 °C, min at -40 to +125 °C 7
Hold time Dn to CP th 5 -2 ns VCC = 4.5 V; see Fig. 7; typ at 25 °C, min at -40 to +125 °C 7
Maximum clock frequency fmax 4 23 MHz VCC = 2.0 V; see Fig. 7; typ at 25 °C, min at -40 to +125 °C 7
Maximum clock frequency fmax 20 70 MHz VCC = 4.5 V; see Fig. 7; typ at 25 °C, min at -40 to +125 °C 7
Maximum clock frequency fmax 24 83 MHz VCC = 6.0 V; see Fig. 7; typ at 25 °C, min at -40 to +125 °C 7

CAD (KiCad official)

  • Symbol: 74HC374PW
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: 74hc374pw-etched.step / 74hc374pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 74hc374pw.step / 74hc374pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nexperia datasheet (15 pp, sha256 bc22298983ba7db8, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF