component
74HC374M
Public Made by Adomby adom
HGSEMI Flip Flops, SOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
74HC374M
HGSEMI · Flip Flops · SOP-20
74HC374M from HGSEMI, in a SOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-LOW output enable input; a HIGH level forces Q0 to Q7 into the high-impedance OFF-state without changing the flip-flop contents. |
| 2 | Q0 | output | Non-inverting 3-state data output of flip-flop 0, high-impedance when OE is HIGH. |
| 3 | D0 | input | Data input to flip-flop 0, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 4 | D1 | input | Data input to flip-flop 1, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 5 | Q1 | output | Non-inverting 3-state data output of flip-flop 1, high-impedance when OE is HIGH. |
| 6 | Q2 | output | Non-inverting 3-state data output of flip-flop 2, high-impedance when OE is HIGH. |
| 7 | D2 | input | Data input to flip-flop 2, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 8 | D3 | input | Data input to flip-flop 3, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 9 | Q3 | output | Non-inverting 3-state data output of flip-flop 3, high-impedance when OE is HIGH. |
| 10 | GND | power_in | Ground reference, 0 V. |
| 11 | CP | input | Clock input; flip-flops capture their D inputs on the LOW-to-HIGH edge. |
| 12 | Q4 | output | Non-inverting 3-state data output of flip-flop 4, high-impedance when OE is HIGH. |
| 13 | D4 | input | Data input to flip-flop 4, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 14 | D5 | input | Data input to flip-flop 5, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 15 | Q5 | output | Non-inverting 3-state data output of flip-flop 5, high-impedance when OE is HIGH. |
| 16 | Q6 | output | Non-inverting 3-state data output of flip-flop 6, high-impedance when OE is HIGH. |
| 17 | D6 | input | Data input to flip-flop 6, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 18 | D7 | input | Data input to flip-flop 7, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 19 | Q7 | output | Non-inverting 3-state data output of flip-flop 7, high-impedance when OE is HIGH. |
| 20 | VCC | power_in | Supply voltage: 2.0 V to 6.0 V for 74HC374 and 4.5 V to 5.5 V for 74HCT374 (absolute maximum 7.0 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | SOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 3 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 3 | |
| output current | IO | -35 | 35 | mA | -0.5V < VO < VCC+0.5V | 3 | |
| supply current | ICC | 70 | mA | 3 | |||
| ground current | IGND | -70 | mA | 3 | |||
| storage temperature | Tstg | -65 | 150 | ℃ | 3 | ||
| total power dissipation | Ptot | 500 | mW | 3 | |||
| soldering temperature (SOP) | TL | 250 | ℃ | 10s | 3 | ||
| supply voltage (74HC374) | VCC | 2 | 5 | 6 | V | 3 | |
| input voltage | VI | 0 | V | 3 | |||
| output voltage | VO | 0 | V | 3 | |||
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 3 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 3 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 3 | ||
| ambient temperature | Tamb | -40 | 85 | ℃ | 3 | ||
| HIGH-level input voltage | VIH | 1.5 | 1.2 | V | Tamb=25℃; VCC=2.0V | 4 | |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | V | Tamb=25℃; VCC=4.5V | 4 | |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | V | Tamb=25℃; VCC=6.0V | 4 | |
| LOW-level input voltage | VIL | 0.8 | 0.5 | V | Tamb=25℃; VCC=2.0V | 4 | |
| LOW-level input voltage | VIL | 2.1 | 1.35 | V | Tamb=25℃; VCC=4.5V | 4 | |
| LOW-level input voltage | VIL | 2.8 | 1.8 | V | Tamb=25℃; VCC=6.0V | 4 | |
| HIGH-level output voltage | VOH | 1.9 | 2 | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V | 4 | |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V | 4 | |
| HIGH-level output voltage | VOH | 5.9 | 6 | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=6.0V | 4 | |
| HIGH-level output voltage | VOH | 3.98 | 4.32 | V | Tamb=25℃; VI=VIH or VIL; IO=-6.0mA; VCC=4.5V | 4 | |
| HIGH-level output voltage | VOH | 5.48 | 5.81 | V | Tamb=25℃; VI=VIH or VIL; IO=-7.8mA; VCC=6.0V | 4 | |
| LOW-level output voltage | VOL | 0 | 0.1 | V | Tamb=25℃; VI=VIH or VIL; IO=20uA; VCC=2.0V | 4 | |
| LOW-level output voltage | VOL | 0.15 | 0.26 | V | Tamb=25℃; VI=VIH or VIL; IO=6.0mA; VCC=4.5V | 4 | |
| LOW-level output voltage | VOL | 0.16 | 0.26 | V | Tamb=25℃; VI=VIH or VIL; IO=7.8mA; VCC=6.0V | 4 | |
| input leakage current | II | -0.1 | 0.1 | uA | Tamb=25℃; VI=VCC or GND; VCC=6.0V | 4 | |
| OFF-state output current | IOZ | -0.5 | 0.5 | uA | Tamb=25℃; VI=VIH or VIL; VCC=6.0V; VO=VCC or GND | 4 | |
| supply current | ICC | 8 | uA | Tamb=25℃; VI=VCC or GND; IO=0A; VCC=6.0V | 4 | ||
| HIGH-level input voltage | VIH | 1.5 | V | Tamb=-40℃ to +85℃; VCC=2.0V | 5 | ||
| HIGH-level input voltage | VIH | 3.15 | V | Tamb=-40℃ to +85℃; VCC=4.5V | 5 | ||
| HIGH-level input voltage | VIH | 4.2 | V | Tamb=-40℃ to +85℃; VCC=6.0V | 5 | ||
| LOW-level input voltage | VIL | 0.5 | V | Tamb=-40℃ to +85℃; VCC=2.0V | 5 | ||
| LOW-level input voltage | VIL | 1.35 | V | Tamb=-40℃ to +85℃; VCC=4.5V | 5 | ||
| LOW-level input voltage | VIL | 1.8 | V | Tamb=-40℃ to +85℃; VCC=6.0V | 5 | ||
| HIGH-level output voltage | VOH | 1.9 | V | Tamb=-40℃ to +85℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V | 5 | ||
| HIGH-level output voltage | VOH | 4.4 | V | Tamb=-40℃ to +85℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V | 5 | ||
| HIGH-level output voltage | VOH | 5.9 | V | Tamb=-40℃ to +85℃; VI=VIH or VIL; IO=-20uA; VCC=6.0V | 5 | ||
| HIGH-level output voltage | VOH | 3.84 | V | Tamb=-40℃ to +85℃; VI=VIH or VIL; IO=-6.0mA; VCC=4.5V | 5 | ||
| HIGH-level output voltage | VOH | 5.34 | V | Tamb=-40℃ to +85℃; VI=VIH or VIL; IO=-7.8mA; VCC=6.0V | 5 | ||
| LOW-level output voltage | VOL | 0.1 | V | Tamb=-40℃ to +85℃; VI=VIH or VIL; IO=20uA; VCC=2.0V | 5 | ||
| LOW-level output voltage | VOL | 0.33 | V | Tamb=-40℃ to +85℃; VI=VIH or VIL; IO=6.0mA; VCC=4.5V | 5 | ||
| input leakage current | II | -1 | 1 | uA | Tamb=-40℃ to +85℃; VI=VCC or GND; VCC=6.0V | 5 | |
| OFF-state output current | IOZ | -5 | 5 | uA | Tamb=-40℃ to +85℃; VI=VIH or VIL; VCC=6.0V; VO=VCC or GND | 5 | |
| supply current | ICC | 80 | uA | Tamb=-40℃ to +85℃; VI=VCC or GND; IO=0A; VCC=6.0V | 5 | ||
| CP to Qn propagation delay | tpd | 41 | ns | Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 6 | 7 | ||
| OE to Qn enable time | ten | 38 | ns | Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 7 | 7 | ||
| OE to Qn disable time | tdis | 38 | ns | Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 7 | 7 | ||
| CP pulse width | tW | 20 | ns | Tamb=-40℃ to +85℃; CP HIGH or LOW; VCC=4.5V; see Figure 6 | 7 | ||
| Dn to CP set-up time | tsu | 15 | ns | Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 6 | 7 | ||
| maximum frequency (CP input) | fmax | 24 | MHz | Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 6 | 7 |
CAD (KiCad official)
- Symbol:
74HC374M - Footprint:
Package_SO:SOP-20_7.5x12.8mm_P1.27mm - 3D model: SOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
74hc374m-etched.step/74hc374m-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hc374m.step/74hc374m.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (13 pp, sha256
65a9aee11bb6e61e, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# 74HC374M
**HGSEMI** · Flip Flops · SOP-20
74HC374M from HGSEMI, in a SOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | Active-LOW output enable input; a HIGH level forces Q0 to Q7 into the high-impedance OFF-state without changing the flip-flop contents. |
| 2 | Q0 | output | Non-inverting 3-state data output of flip-flop 0, high-impedance when OE is HIGH. |
| 3 | D0 | input | Data input to flip-flop 0, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 4 | D1 | input | Data input to flip-flop 1, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 5 | Q1 | output | Non-inverting 3-state data output of flip-flop 1, high-impedance when OE is HIGH. |
| 6 | Q2 | output | Non-inverting 3-state data output of flip-flop 2, high-impedance when OE is HIGH. |
| 7 | D2 | input | Data input to flip-flop 2, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 8 | D3 | input | Data input to flip-flop 3, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 9 | Q3 | output | Non-inverting 3-state data output of flip-flop 3, high-impedance when OE is HIGH. |
| 10 | GND | power_in | Ground reference, 0 V. |
| 11 | CP | input | Clock input; flip-flops capture their D inputs on the LOW-to-HIGH edge. |
| 12 | Q4 | output | Non-inverting 3-state data output of flip-flop 4, high-impedance when OE is HIGH. |
| 13 | D4 | input | Data input to flip-flop 4, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 14 | D5 | input | Data input to flip-flop 5, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 15 | Q5 | output | Non-inverting 3-state data output of flip-flop 5, high-impedance when OE is HIGH. |
| 16 | Q6 | output | Non-inverting 3-state data output of flip-flop 6, high-impedance when OE is HIGH. |
| 17 | D6 | input | Data input to flip-flop 6, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 18 | D7 | input | Data input to flip-flop 7, stored on the LOW-to-HIGH clock transition if set-up and hold times are met; inputs include clamp diodes for use with current-limiting resistors above VCC. |
| 19 | Q7 | output | Non-inverting 3-state data output of flip-flop 7, high-impedance when OE is HIGH. |
| 20 | VCC | power_in | Supply voltage: 2.0 V to 6.0 V for 74HC374 and 4.5 V to 5.5 V for 74HCT374 (absolute maximum 7.0 V). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | SOP-20 |
| Category | Logic |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | | 7 | V | | 3 |
| input clamping current | IIK | -20 | | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 3 |
| output clamping current | IOK | -20 | | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 3 |
| output current | IO | -35 | | 35 | mA | -0.5V < VO < VCC+0.5V | 3 |
| supply current | ICC | | | 70 | mA | | 3 |
| ground current | IGND | -70 | | | mA | | 3 |
| storage temperature | Tstg | -65 | | 150 | ℃ | | 3 |
| total power dissipation | Ptot | | | 500 | mW | | 3 |
| soldering temperature (SOP) | TL | | | 250 | ℃ | 10s | 3 |
| supply voltage (74HC374) | VCC | 2 | 5 | 6 | V | | 3 |
| input voltage | VI | 0 | | | V | | 3 |
| output voltage | VO | 0 | | | V | | 3 |
| input transition rise and fall rate | Δt/ΔV | | | 625 | ns/V | VCC=2.0V | 3 |
| input transition rise and fall rate | Δt/ΔV | | 1.67 | 139 | ns/V | VCC=4.5V | 3 |
| input transition rise and fall rate | Δt/ΔV | | | 83 | ns/V | VCC=6.0V | 3 |
| ambient temperature | Tamb | -40 | | 85 | ℃ | | 3 |
| HIGH-level input voltage | VIH | 1.5 | 1.2 | | V | Tamb=25℃; VCC=2.0V | 4 |
| HIGH-level input voltage | VIH | 3.15 | 2.4 | | V | Tamb=25℃; VCC=4.5V | 4 |
| HIGH-level input voltage | VIH | 4.2 | 3.2 | | V | Tamb=25℃; VCC=6.0V | 4 |
| LOW-level input voltage | VIL | | 0.8 | 0.5 | V | Tamb=25℃; VCC=2.0V | 4 |
| LOW-level input voltage | VIL | | 2.1 | 1.35 | V | Tamb=25℃; VCC=4.5V | 4 |
| LOW-level input voltage | VIL | | 2.8 | 1.8 | V | Tamb=25℃; VCC=6.0V | 4 |
| HIGH-level output voltage | VOH | 1.9 | 2 | | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V | 4 |
| HIGH-level output voltage | VOH | 4.4 | 4.5 | | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V | 4 |
| HIGH-level output voltage | VOH | 5.9 | 6 | | V | Tamb=25℃; VI=VIH or VIL; IO=-20uA; VCC=6.0V | 4 |
| HIGH-level output voltage | VOH | 3.98 | 4.32 | | V | Tamb=25℃; VI=VIH or VIL; IO=-6.0mA; VCC=4.5V | 4 |
| HIGH-level output voltage | VOH | 5.48 | 5.81 | | V | Tamb=25℃; VI=VIH or VIL; IO=-7.8mA; VCC=6.0V | 4 |
| LOW-level output voltage | VOL | | 0 | 0.1 | V | Tamb=25℃; VI=VIH or VIL; IO=20uA; VCC=2.0V | 4 |
| LOW-level output voltage | VOL | | 0.15 | 0.26 | V | Tamb=25℃; VI=VIH or VIL; IO=6.0mA; VCC=4.5V | 4 |
| LOW-level output voltage | VOL | | 0.16 | 0.26 | V | Tamb=25℃; VI=VIH or VIL; IO=7.8mA; VCC=6.0V | 4 |
| input leakage current | II | -0.1 | | 0.1 | uA | Tamb=25℃; VI=VCC or GND; VCC=6.0V | 4 |
| OFF-state output current | IOZ | -0.5 | | 0.5 | uA | Tamb=25℃; VI=VIH or VIL; VCC=6.0V; VO=VCC or GND | 4 |
| supply current | ICC | | | 8 | uA | Tamb=25℃; VI=VCC or GND; IO=0A; VCC=6.0V | 4 |
| HIGH-level input voltage | VIH | 1.5 | | | V | Tamb=-40℃ to +85℃; VCC=2.0V | 5 |
| HIGH-level input voltage | VIH | 3.15 | | | V | Tamb=-40℃ to +85℃; VCC=4.5V | 5 |
| HIGH-level input voltage | VIH | 4.2 | | | V | Tamb=-40℃ to +85℃; VCC=6.0V | 5 |
| LOW-level input voltage | VIL | | | 0.5 | V | Tamb=-40℃ to +85℃; VCC=2.0V | 5 |
| LOW-level input voltage | VIL | | | 1.35 | V | Tamb=-40℃ to +85℃; VCC=4.5V | 5 |
| LOW-level input voltage | VIL | | | 1.8 | V | Tamb=-40℃ to +85℃; VCC=6.0V | 5 |
| HIGH-level output voltage | VOH | 1.9 | | | V | Tamb=-40℃ to +85℃; VI=VIH or VIL; IO=-20uA; VCC=2.0V | 5 |
| HIGH-level output voltage | VOH | 4.4 | | | V | Tamb=-40℃ to +85℃; VI=VIH or VIL; IO=-20uA; VCC=4.5V | 5 |
| HIGH-level output voltage | VOH | 5.9 | | | V | Tamb=-40℃ to +85℃; VI=VIH or VIL; IO=-20uA; VCC=6.0V | 5 |
| HIGH-level output voltage | VOH | 3.84 | | | V | Tamb=-40℃ to +85℃; VI=VIH or VIL; IO=-6.0mA; VCC=4.5V | 5 |
| HIGH-level output voltage | VOH | 5.34 | | | V | Tamb=-40℃ to +85℃; VI=VIH or VIL; IO=-7.8mA; VCC=6.0V | 5 |
| LOW-level output voltage | VOL | | | 0.1 | V | Tamb=-40℃ to +85℃; VI=VIH or VIL; IO=20uA; VCC=2.0V | 5 |
| LOW-level output voltage | VOL | | | 0.33 | V | Tamb=-40℃ to +85℃; VI=VIH or VIL; IO=6.0mA; VCC=4.5V | 5 |
| input leakage current | II | -1 | | 1 | uA | Tamb=-40℃ to +85℃; VI=VCC or GND; VCC=6.0V | 5 |
| OFF-state output current | IOZ | -5 | | 5 | uA | Tamb=-40℃ to +85℃; VI=VIH or VIL; VCC=6.0V; VO=VCC or GND | 5 |
| supply current | ICC | | | 80 | uA | Tamb=-40℃ to +85℃; VI=VCC or GND; IO=0A; VCC=6.0V | 5 |
| CP to Qn propagation delay | tpd | | | 41 | ns | Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 6 | 7 |
| OE to Qn enable time | ten | | | 38 | ns | Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 7 | 7 |
| OE to Qn disable time | tdis | | | 38 | ns | Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 7 | 7 |
| CP pulse width | tW | 20 | | | ns | Tamb=-40℃ to +85℃; CP HIGH or LOW; VCC=4.5V; see Figure 6 | 7 |
| Dn to CP set-up time | tsu | 15 | | | ns | Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 6 | 7 |
| maximum frequency (CP input) | fmax | 24 | | | MHz | Tamb=-40℃ to +85℃; VCC=4.5V; see Figure 6 | 7 |
## CAD (KiCad official)
- Symbol: `74HC374M`
- Footprint: `Package_SO:SOP-20_7.5x12.8mm_P1.27mm`
- 3D model: SOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `74hc374m-etched.step` / `74hc374m-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74hc374m.step` / `74hc374m.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [HGSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603132480627228672) (13 pp, sha256 `65a9aee11bb6e61e`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/74hc374m-datasheet.pdf)